Transcript Domain wall clocking

IBM Research
Contact
Reinier A. van Mourik, MSc
PhD Researcher
Spintronics Devices
IBM / Eindhoven University of Technology
IBM Almaden Research Center
650 Harry Rd
San Jose, CA 95120
USA
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+1 408 927 2501
+1 408 927 2510
+1 408 821 4559
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Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
© 2013 IBM Corporation
Reinier van Mourik1,2, Li Gao1, Brian Hughes1, Charles Rettner1, Bert Koopmans2, Stuart Parkin1
1. IBM Almaden Research Center, San Jose, CA
2. Eindhoven University of Technology, Eindhoven, the Netherlands
Reliability of Signal Propagation in
Magnetostatically Coupled Arrays of
Magnetic Nanoelements
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
© 2013
IBM
© 2009
IBMCorporation
Corporation
IBM Research
Nanomagnetic logic - principle
Majority gate
A
M
B
D
1. Introduction
output read
•
•
•
•
Energy-efficient
Non-volatile
Fast
Radiation resistant
C
A
B
M
D
C
Majority gate is
programmable NAND/NOR
gate  Full logic set
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
© 2013 IBM Corporation
IBM Research
Outline
 Experiment and simulation: inherent
unreliability
1. Introduction
 Alternative for conventional NML: Domain
wall clocking
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
© 2013 IBM Corporation
IBM Research
Experiment setup
 fabrication
 measurement
10.0
d916
9.5
Resistance (k)
9.0
8.5
Reset:
o
0
o
180
~70Oe
8.0
7.5
2. Error rate in NML devices
7.0
6.5
-150
-100
-50
0
50
Field (Oe)
The RH curve of the MTJ
shows output of device
Artificial input biases first dot
according to reset direction
d514
MFM shows state of each dot
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
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IBM Research
Single device: shot-to-shot results
R (k)
12
11
10
9
0
100
200
300
400
500
600
700
800
input
12
R (k)
2. Error rate in NML devices
Cycles (#)
11
output
10
9
0
100
Cycles (#)
Output MTJ state alternates accordingly when alternating input direction.
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
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IBM Research
Many devices: device-to-device results
clocking cycle, input +x
2. Error rate in NML devices
 68/158 (43%) of devices contain
errors
repeat clocking cycle, input +x
 116/123 (94%) of devices
evolve to exact same state
clocking cycle, input -x
 66/79 (84%) of devices
evolve to exact inverse
state
Success/error is highly reproducible, thus inherent in device.
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
© 2013 IBM Corporation
IBM Research
2. Error rate in NML devices
Error rate in signal propagation - simulations
 Device-to-device error rate tends
to 50% as length increases
 Last NM evolves before signal
reaches it
Errors are caused by last magnet evolving early.
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
© 2013 IBM Corporation
IBM Research
3. Domain wall clocking
Domain wall clocking - principle
Fringing field from domain wall in perpendicularly magnetized material can
reset nanomagnets.
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
© 2013 IBM Corporation
IBM Research
DW clocking – experimental setup
DW
nanodots Py 60x90x20nm
Hall bar
Domain wall injection line
1. inject DW
hall bar
read
PMA nanowire 60-180nm wide
𝑀
𝑀
𝐻
3. Domain wall clocking
2. propagate DW by H field
3. read resistance change
in AMR and Hall bar
AMR read
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
© 2013 IBM Corporation
IBM Research
DW clocking - results
3. Domain wall clocking
Prepare device in
incorrect state
Pass DW
underneath
End in correct
state
DW clocking demonstrated in 1- and 2-magnet devices
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
© 2013 IBM Corporation
IBM Research
Conclusion
 Nanomagnetic Logic is magnetic alternative to
CMOS logic
 Analysis done of reliability of NML devices with
integrated output
 Errors are reproducible per device and tend to
50% among devices.
 Domain Wall clocking is demonstrated as
alternative clocking scheme
slides & contact: http://tinyurl.com/RvM-IBM
Nanomagnetic Logic | Mar 18 2013 | IBM/TUe
© 2013 IBM Corporation