Transcript KBC

LWG2 Power Sequence Introduce
Prepared By: Withy He
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2
DC-DC Source
BT+
AD+
DCBATOUT
MOS
S5
U4
U5
MOS
EC_PWRBTN#
5V_AUX_S5
3D3V_AUX_S5
EN1_5
KBC
U45
S5_EN
5V_S5
3D3V_S5
EN2_3D3 POK
S3
PM_SLP_S5#
1D8V_S3
U44
DDR_VREF_S3
U74
S0
PM_SLP_S3#
ICH7-M
U51
U52
U27
5V_S0
3D3V_S0
1D8V_S0
U6
2D5V_S0
U74
POK
POK
CPUCORE_ON
3
DDR_VREF_S0
U44
U22
U25
1D05V_S0
1D5V_S0
VCC_CORE_S0
Charger Circuit
DCBATOUT
AD+
ACIN
ACOK
DCBATOUT
BT+
SW
MODE
BATA_IN#
KBC
4
Charge
PKPRES#
Circuit
MAX8725
CHG_V_PWM
VCTL
CHG_I_PWN
ICTL
DHI
DLO
CSIP
CSIN
CONTROL
FEEDBACK
Power On/Reset Step
1.Adapter In:
Adapter In
MOS
AD+
MOS
DCBATOUT LP2951 5V_AUX_S5 G913
3D3V_AUX_S5
KBC
BT+
H8_RESET#
ICH
MOS
RTC_AUX_S5
RE144B
2.Power On:
EC_PWRBTN#
PWRBTN#_ICH
KBC
RE144B
S5_EN
TPS51120
RSMRST#_TO_KBC
SB_RSMRST#
5
5V_S5
3D3V_S5
ICH
3.S3:
PM_SLP_S5#
ICH
TPS51124
TPS51100
1D8V_S3
DDR_VREF_S3
4.S0:
PM_SLP_S3#
ICH
DDR_VREF_S0
TPS51100
MOS
5V_S0
MOS
3D3V_S0
APL5332KAC
MOS
APL5912_KAC
2D5V_S0
1D8V_S0
1D5V_S0
1D05V_S0
TPS51124
6
5.VCC_CORE_S0:
TPS51120
POK
CPUCORE_ON
ISL6262
VCC_CORE_S0
TPS51124
POK
APL5912_KAC
POK
6.System Reset:
CLK GEN
HCPURST#
MCH Calistoga
VTT_PWRGD#
PWROK
RSTIN#
H_CPURST#
H_PWRGD
CLK_EN#
ISL6262
PGOOD
CPUPWRGD
VGATE_PWRGD VRMPWRGD
ICH
PWROK
RESET#
G792
7
PWROK
PLTRST1#
PCIRST#
PLT_RST1#
PCIRST1#
RESET#
CPU
Yonah
PWRGOOD
HDD/CDROM
KBC
DEBUG G.F.
GPU
LAN
TI PCI 7412
Power SW
Power On/Reset Sequence
RTC_AUX_S5
AD_IN/AD+
DCBATOUT
5V_AUX_S5/3.3V_AUX_S5
H8_RESET#
EC_PWRBTN#
S5_EN
3D3V_S5/5V_S5
RSMRST#_TO_KBC
PM_RSMRST#
PM_SLP_S4#
1D8V_S3
DDR_VREF_S3
PM_SLP_S3#
5V_S0,D3V_S0,2D5V_S0,
DDR_VREF_S0
1D8V_S0,1D5V_S0,1D05V_S0
CPUCORE_ON
VCC_CORE_S0
VGATE_PWRGD
CLK_EN#
H_PWRGD
PLT_RST#
PCI_RST#
H_CPURST#
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