Transcript K-S note Power study1

KS NOTE Power Study
NDK100/ PE Jimmy
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Presentation Title
Power table -1
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Presentation Title
Power table -2
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Presentation Title
H8
2
VCCXM_ON
1
PWR_SW
M_ON
VCCXA_ON
aux_ON
A_ON
5
8
B_ON
PMH7
TSURUMA
9
POWER
VCCXB_ON
MPWRGD
BPWRGD
10
7
SLP_S3 . SLP_S4
PCI
DEVICE
4
PWR_SW_H8
PCIRST
PLTRST
SB
BPWRGD
13
12
14
NB
CPU_PWRGD
(BPWRGDX
VR_PWRGD)
CPURST
VR_PWRGD
ADP
3207
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Presentation Title
VCCCPUCORE
11
CPU
15
1. Insert adapter to system
(1) DOCK_PWR19_F&VREGIN19& VCC3SW Power generate process with adapter
U12
CV19
Adapter In
F10
Dock_PWR19_F
F14
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Presentation Title
VREGIN19
VCC3SW
Input
output
VREGIN19
U74
VCC3SW
因此只要power VREGIN19 supply to U74 , 無須控制信號U74產生VCC3SW
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Presentation Title
VINT19
CV19
U13
VINT19
When DCIN_DRV=H, 打開 U13 and generate
VINT19
DOCK_PWR19_F
&VREGIN19& VCC3SW Power Sequence
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Presentation Title
Power on Enable signal generate
DOCK_PWR19
when adapter insert and U64 detect AC power OK , then generate EXTPWR.
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Presentation Title
VINT19
EXTPWR_PMH generate process and Power Sequence
EXTPWR 信號 be sent to Q50 產生EXTPWR_PMH .
Of course , system need Power VL5 來打開Q50 .
VL5 generate process as next page:
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Presentation Title
VL5
VINT19
U58
MAX1977_LOD5
R189
When U58 detect VINT19 OK , 產生
MAX1977_LCDO5 , 再通過R189產生VL5
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Presentation Title
Vl5
M1_ON & M2_ON&AUX_ON
EXTPWR_PMH
M1_ON
U72
M2_ON
EXTPWR_PMH
PWH7
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Presentation Title
AUXON
Control Signal EXTPWR_PMH be sent to U72 ,
然后產生Control Signal M1_ON/M2_ON/AUX_ON
M1_ON & M2_ON&AUX_ON Sequence
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Presentation Title
PWH Control Signal Sequence
這里順便了解一下PWH Control Signal Sequence
(1)
System detect EXTPWR OK then generate M_ON & AUX_ON
(2)
System detect PWRSTWITCH OK then generate A_ON &B_ON ,
也就是說﹕
System generate M_ON & AUX_ON before pressing power button
System generate A_ON & B_ON after pressing power button
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Presentation Title
VCC3M_ON & VCC5M_ON & VCC1R5M_ON & VCC1R2AUX_ON & VCC3AUX_ON
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Presentation Title
VCC3M & VCC5M
Output VCC3M
Output VCC5M
Enable Signal : VCC5M_ON
VINT19
VCC5M_ON
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Presentation Title
U58
Max1977
VCC3M&VCC5M
VCC3M & VCC5M Sequence
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Presentation Title
MPWRG
VCC5M
VCC3M
When U74 detect VCC3M&VCC5M
all OK , then it send MPWRG
VCC3M&VCC5M
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VREGIN19
Presentation Title
U74
BD4175KVT
MPWRG
MPWRG Sequence
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Presentation Title
MPWRG Signal
generate high signal when the following condition are satisfied.
(1) VCC3M_ON& VCC5M_ON High
(2) VCC5M Voltage SPEC: 4.311V~4.461V
VCC3M Voltage SPEC : 2.793V~2.943V
shut down when the following condition are satisfied
(3) VCC5M < 4.311V or VCC5M > 4.461V , M_PGS shut down
(4) VCC3M> 2.943V or VCC3M< 2.793V , M_PGS shut t down
5M_ON & 3M_ON
AND
VCC3M&VCC5M
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Presentation Title
M_PGS
VCC1R5M
Power
Output
Control signal
VCC5M&VINT19
VCC1R5M_ON
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Presentation Title
U57
Max1540
VCC1R5M
VCC1R5M Sequence
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Presentation Title
VCC1R2AUX
VCC1R2AUX_ON
VCC1R5M
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Presentation Title
U35
VCC1R2AUX
VCC1R2AUX Sequence
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Presentation Title
VCC2R5M
U30
VCC3M
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Presentation Title
VCC2R5M
VCC2R5AUX & VCC3AUX
VCC2R5M
VCC3AUX_ON
VREGIN19
U74
Presentation Title
VCC2R5AUX
Q49
VCC3AUX
VCC3AUX_DRV
VCC3M
25
Q46
VCC2R5AUX & VCC3AUX Sequence
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Presentation Title
Summary
以上介紹的Power 是在 Adapter insert system but do not power on 產生的 ,
下面介紹Power on 后系統的上電情況.
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Presentation Title
2.
Power
On
PWRSWITCH# & PWRSW# & PWRSW_H8#
D10
Press Power Button
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Presentation Title
PWRSWITCH#
PWRSW#
KBC
PWRSW_H8#
PWRSWITCH# & PWRSW# & PWRSW_H8# Sequence
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Presentation Title
Enable signal Diagram
PM_SLP_S3#
5
PM_SLP_S3#
1
A1_ON
PWRSWITCH
PWH7
B1_ON
5
B2_ON
ICH_SLP_S3#
D10
4
ICH_SLP_S4#
2
PWRSW
KBC
PWRSW_H8
3
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Presentation Title
ICH7
ICH_SLP_S3# & ICH_SLP_S4# & PM_SLP_S3# & PM_SLP_S5# Sequence
ICH_SLP_S3# & ICH_SLP_S4# Sequence
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Presentation Title
PM_SLP_S3# & PM_SLP_S5# Sequence
A1_ON & B1_ON & B2_ON Sequence
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Presentation Title
VCC1R8A_ON & VCC1R05B_ON & B_ON & VCC0R9B_ON
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Presentation Title
VCC1R8A
Power
Output
Control Signal
VCC5M & VINT19
VCC1R8A_ON
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Presentation Title
U21
VCC1R8A
VCC1R8A Sequence
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Presentation Title
VCC1R05B
VINT19&VCC5M
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Presentation Title
VCC1R05B_ON
U57
VCC1R05B
VCC0R9B & VREF
Power
Output
Control Signal
VCC1R8A&VCC5M
VCC0R9B_ON
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Presentation Title
VCC0R9B
U21
DDR2_VREF
VCC2R5B
B_ON
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Presentation Title
U74
VCC2R5B_DRV
Q39
VCC2R5B
VCC0R9B & VCC1R05B & VCC2R5B
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Presentation Title
VCC3B & VCC5B
B_ON 通過U74將Q67&Q52打開 to generate VCC3B&VCC5B
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Presentation Title
VCC1R5B
U75
B_ON
VCC2R5B_DRV
VCC1R5M
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Presentation Title
U60
VCC1R5B
VCCCPUCORE_ON
If VCC1R05B & VCC1R5M OK then VTT_PWRG turn high
VTT_PWRG
B2_ON
SHUTDOWN2
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Presentation Title
AND
VCORE_ON
VCCCPUCORE
If VCCCPUCORE OK , then generate VR_PWRGD
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Presentation Title
VCCCPUCORE Sequence
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Presentation Title
B POWER & VCCCPUCORE Sequence
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Presentation Title
MPWRG & APWRG & BPWRG
If VCC3M/VCC5M & VCC3A & VCC3B/VCC5B OK , then pull high MPWRG & APWRG & BPWRG
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Presentation Title
MPWRG & APWRG & BPWRG Sequence
Spec:
APWRG to BPWRG is
80-120ms
80-120ms
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Presentation Title
PCIRST# CPURST#
CPUPWRGD=VR_PWRGD AND BPWRG
2
VR_PWRGD
PCIRST
2
ICH7
1
CPUPWRGD
BPWRG
PLTRST
ADS
CPU
3
CALISTOGA
7
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CPURST
7
Presentation Title
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