Transcript KS NOTE Power Sequence

KS NOTE Power Sequence
NDK100 : Jimmy Chen
KS Note Block Diagram
Power Block Diagram
H8
2
VCCXM_ON
PWR_SW
5
B_ON
MPWRGD
BPWRGD
6
SLP_S3 . SLP_S4
VCCXA_ON
TSURUMA
A_ON
PMH7
8
1
M_ON
PCI
DEVICE
PWR_SW_H8
PCIRST
PLTRST
BPWRGD
12
11
VCCXB_ON
7
3
9
4
SB
13
NB
CPU_PWRGD
(BPWRGDX
VR_PWRGD)
CPURST
VR_PWRGD
ADP
3207
VCCCPUCORE
10
POWER
CPU
14
Power sequence Table-1
Power sequence Table-2
DOCK-PWR19-F
VREGIN19
U12 pin 1,2,3
DOCK-PWR19-F=> D41 pin3
U12 pin 1,2,3
D41 pin3
VREGIN19
VCC3SW
CV19
VINT19
EXTPWR_PMH
DOCK-PWR19-F=> D41 pin3
Output from U74 pin 59
DOCK-PWR19-F => U12 Pin5,6,7,8
CV19 => U13 pin 5,6,7,8
to detect AC
VREGIN19
D41 pin3
C440 pin1
U12 Pin5,6,7,8
U13 pin 5,6,7,8
R411 pin 2
U74
VCC3SW
因此只要power VREGIN19 supply to U74 , 無須控制信號
U74產生VCC3SW
EXTPWR_PMH
M1_ON
M2_ON
to detect AC
Output from PWH7 pin76 to enable M power
Output from PWH7 pin43
R411 pin 2
R469 pin1
R435 pin1
M1_ON
U72
EXTPWR_PMH
M2_ON
PWH7
AUXON
Control Signal EXTPWR_PMH be sent to U72 ,
然后產生Control Signal M1_ON/M2_ON/AUX_ON
這里順便了解一下PWH Control Signal Sequence
(1)
System detect EXTPWR OK then generate M_ON & AUX_ON
(2)
System detect PWRSTWITCH OK then generate A_ON &B_ON ,
也就是說﹕
System generate M_ON & AUX_ON before pressing power button
System generate A_ON & B_ON after pressing power button
M1_ON
VCC3M_ON
VCC5M_ON
Output from PWH7 pin76 to enable M power
M1_ON => VCC3M_ON
M1_ON => VCC5M_ON
R469 pin1
R480 pin2
R469 pin2
VCC3M_ON
VCC3M
VCC2R5M
VCC5M_ON
VCC5M
M1_ON => VCC3M_ON
output from U58 pin 15
VCC3M=>VCC2R5M
M1_ON => VCC5M_ON
output from U58 pin 27
R480 pin2
TC4 pin1
C366 pin1
R469 pin2
TC13 pin1
VCC3M
VCC5M
MPWRG
output from U58 pin 15
output from U58 pin 27
Output from U74 pin 51 to detect M power OK
TC4 pin1
TC13 pin1
R479 pin2
M2_ON
Output from PWH7 pin43
R435 pin1
VCC1R5M_ON
M2_ON => VCC1R5M_ON
Output from U57 pin15
R435 pin2
TC17 pin1
VCC1R5M
VCC3M
VCC5M
MPWRG
output from U58 pin 15
output from U58 pin 27
Output from U74 pin 51 to detect M power OK
TC4 pin1
TC13 pin1
R479 pin2
AUX_ON
VCC1R2AUX_ON
VCC3AUX_ON
Output from PWH7 pin88 to enable AUX power
AUX_ON => VCC1R2AUX_ON
AUX_ON => VCC3AUX_ON
R367 pin1
R367 pin2
R365 pin2
AUX_ON
VCC1R2AUX_ON
VCC1R2AUX
Output from PWH7 pin88 to enable AUX power
AUX_ON => VCC1R2AUX_ON
VCC1R5M=>VCC1R2AUX
R367 pin1
R367 pin2
C464 pin1
VCC3AUX_ON
VCC3AUX
VCC2R5AUX
AUX_ON => VCC3AUX_ON
VCC3M => VCC3AUX
VCC3M=>VCC2R5M=>VCC2R5AUX
R365 pin2
Q49 pin2
C472pin1
MPWRG
ICH_SLP_S3#
ICH_SLP_S4#
Output from U74 pin 51 to detect M power OK
Output from ICH7
Output from ICH7
R479 pin2
U72 pin20
U72 pin74
PWRSWITCH#
PM_SLP_S3#
PM_SLP_S4#
press power button , output from CN3 pin19
Output from PWH7
Output from PWH7
D10 pin 1
Q59 pin3
U72 pin 72
PWRSWITCH#
A1_ON
B1_ON
B2_ON
press power button , output from CN3 pin19
Output from PWH7
Output from PWH7
Output from PWH7
D10 pin 1
R436 pin1
R475 pin1
D2 pin2
A1_ON
VCC1R8A_ON
VCC1R8A
Output from PWH7
A1_ON=>VCC1R8A_ON
VCC5M=>VCC1R8A
R436 pin1
R426 pin2
C195 pin1
B1_ON
B_ON
VCC0R9B_ON
VCC1R05B_ON
Output from PWH7
B1_ON=> B_ON
B1_ON=>VCC0R9B_ON
B1_ON=>VCC1R05B_ON
R475 pin1
R490 pin2
R491 pin2
R475 pin2
B_ON
VCC3B
VCC5B
B1_ON=> B_ON
VCC3M=>VCC3B
VCC5M=>VCC5B
R490 pin2
Q67 pin4
Q52 pin4
B_ON
VCC0R9B_ON
VCC0R9B
B1_ON=> B_ON
B1_ON=>VCC0R9B_ON
VCC5M=>VCC0R9B
R490 pin2
R491 pin2
C197 pin1
B_ON
VCC1R05B_ON
VCC1R05B
B1_ON=> B_ON
B1_ON=>VCC1R05B_ON
VCC5M=>VCC1R05B
R490 pin2
R475 pin2
C239 pin2
B_ON
VCC1R5B
B1_ON=> B_ON
VCC1R5M=>VCC1R5B
R490 pin2
U60 pin1,2,3
B2_ON
VCCCPUCORE
VR_PWRGD
Output from PWH7
Output from U44
Detect VCCCPUCORE
D2 pin2
C105 pin 1
R175 pin1
VR_PWRGD
BPWRG(PWROK)
CPUPWRGD
Detect VCCCPUCORE
Detect B power
VR_PWRGD & BPWRG
R175 pin1
U74 pin50
R82 pin2
CPUPWRGD
PCIRST#
CPURST#
VR_PWRGD & BPWRG
output from ICH7 to reset the device that reset on PCI bus
output from NB to enable CPU
R82 pin2
R696 pin 2
R70 pin2