Transcript 32bit的位址匯流排Data HWDATA[31:0]

An Efficient SoC Test Technique by
Reusing On/Off-Chip Bus Bridge
Adviser:
Chao-Lieh Chen
Student:
Shih-Hao Lin
Yi-Ming Huang
Keng-Chih Liu
0052802
0052811
0052810
Outline








Introduction
Proposed TAM for AMBA-based SOC
Proposed Test-Access Architecture
On/Off-Chip Bus Bridge With Test Controllability
Operation of the TR-Bridge
Project
Schedule
Division of work
Introduction
Proposed TAM for AMBA-based SOC




The main contribution of our technique is to reuse the on/off
chip bus bridge as a test interface during the test mode.
The AHB master component on the bridge is reused as an
interface between the ATE and the chip under test, and then,
the ATE acts as a virtual bus master.
By utilizing the functional buses as dedicated test paths and
eliminating the bus-direction turnaround delays.
In this paper, the bridge with the test controllability is referred to
as a test-ready bridge.
Proposed Test-Access Architecture
On/Off-Chip Bus Bridge With Test
Controllability
On/Off-Chip Bus Bridge With Test
Controllability
Operation of the TR-Bridge
Project

Midterm project
AHB bus

Final project
Hybrid Test Interface Controller
Schedule
Date
Progress
Date
Progress
10/25
Propose paper
12/06 Implement final project
11/01
Implement midterm project
12/13 Implement final project
11/08
Simulation
12/20 Simulation
11/15
Implement final project
12/27 Test final project
11/22
Implement final project
01/03 Test final project
11/29
Implement final project
01/10 Demo result
Division of work

Shih-Hao Lin
撰寫程式實現HTIC區塊

Yi-Ming Huang
撰寫程式實現AHB Master區塊

Keng-Chih Liu
搜尋實現過程中之相關資訊
期中專案
HTIC 腳位定義
腳位名稱
Bit數
說明
TCLK
1 Bit
clock
TREQ
1 Bit
測試要求
TACK
1 Bit
測試確認
CBE
3 Bit
00:Control 01:Write
10:Read
11:Address
Master Input 腳位定義
Master Input腳位名稱
Bit數
說明
HRESETn
1 Bit
reset
HCLK
1 Bit
clock
HGRANTx
1 Bit
Arbiter grant
HREADY
1 Bit
Transfer response
HRESP[1:0]
2 Bit
Transfer response
00表示完成,01表示err,10表示again,11
表示分割傳送
HRDATA[31:0]
32 Bit
32bit的位址匯流排 Data
Master Onput腳位定義
Master Onput腳位名稱
Bit數
說明
HBUSREQx
1 Bit
向仲裁者Arbiter要求使用匯流排的
訊號腳
HLOCKx
1 Bit
Arbiter
HTRANS[1:0]
2 Bit
2bit的狀態訊號 : 00為IDLE,01為忙
碌,10為第1筆資料,11為非第1筆資料
HWRITE
1 Bit
讀寫控制線 1為寫入 0為讀取
HSIZE[2:0]
3 Bit
傳輸DATA大小之設定,常見有
byte(8-bit),halfword(16bit),word(32-bit)這3種
HBURST[2:0]
3 Bit
傳輸DATA模式之設定,
有單筆和多筆模式,多筆模式有分成1
次傳輸4筆,8筆,16筆
HPROT[3:0]
4 Bit
HADDR[31:0]
32 Bit
Address and control
32bit的位址匯流排 Data
HWDATA[31:0]
32 Bit
32bit的位址匯流排 Data
Slave Input腳位定義
Slave Input腳位名稱
Bit數
說明
HRESETn
1 Bit
reset
HCLK
1 Bit
clock
HSELx
1 Bit
select
HTRANS[1:0]
2 Bit
2bit的狀態訊號 : 00為IDLE,01為忙
碌,10為第1筆資料,11為非第1筆資料
HWRITE
1 Bit
讀寫控制線 1為寫入 0為讀取
HSIZE[2:0]
3 Bit
傳輸DATA模式之設定,
有單筆和多筆模式,多筆模式有分成1次傳
輸4筆,8筆,16筆
HBURST[2:0]
3 Bit
傳輸DATA模式之設定,
有單筆和多筆模式,多筆模式有分成1次傳
輸4筆,8筆,16筆
HADDR[31:0]
32 Bit
32bit的位址匯流排 Data
HWDATA[31:0]
32 Bit
32bit的位址匯流排 Data
HMASTER[3:0]
4 Bit
Slave Onput腳位定義
Slave Onput腳位名稱
Bit數
說明
HREADY
1 Bit
匯流排轉讓訊號,1為處理完成,0為須再
延遲1個cycle
HRESP[1:0]
1 Bit
2個bit的處理狀態
00為傳送完成,01為傳送錯誤,10為要求
Master再傳送一次,11為資料傳送需要
分割的方式來傳送,並釋放匯流排的使
用權限
HRDATA[31:0]
32 Bit
32bit的位址匯流排 Data
HSPLITx[15:0]
16 Bit
16bit的分割編號,讓Arbiter知道要讓哪
個Master完成分割傳送
Master 有限狀態機
Slave 有限狀態機
HTIC 有限狀態機
模擬結果