VLSI Interconnects
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Transcript VLSI Interconnects
VLSI Interconnects
Instructed by Shmuel Wimer
Eng. School, Bar-Ilan University
Credits: David Harris
Harvey Mudd College
(Some material copied/taken/adapted from
Harris’ lecture notes)
Dec 2010
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Outline
Introduction
Wire Resistance
Wire Capacitance
Wire RC Delay
Crosstalk
Wire Engineering
Repeaters
Scaling
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Introduction
Chips are mostly made of wires called interconnect
Alternating layers run orthogonally
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Transistors are little things under the wires
Many layers of wires
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Wires are as important as transistors
– Speed
– Power
– Noise
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Wire Geometry
Pitch = w + s
Aspect ratio: AR = t/w
– Old processes had AR << 1
– Modern processes have AR 2
• Pack in many skinny wires
w
s
l
t
h
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Layer Stack
Modern processes use 6-10+ metal layers
Example: Intel 180 nm process
M1: thin, narrow (< 3l)
– High density cells
M2-M4: thicker
– For longer wires
M5-M6: thickest
– For VDD, GND, clk
Layer
T(nm)
W(nm) S (nm)
AR
6
1720
860
860
2.0
5
1600
800
800
2.0
4
1080
540
540
2.0
3
700
320
320
2.2
2
700
320
320
2.2
1
480
250
250
1.9
Substrate
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Wire Resistance
r = resistivity (W*m)
r l
l
R
R
t w
w
R = sheet resistance (W/)
– is a dimensionless unit(!)
Count number of squares
– R = R * (# of squares)
w
l
w
l
t
l
t
1 Rectangular Block
R = R (L/W) W
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w
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4 Rectangular Blocks
R = R (2L/2W)W
= R (L/W) W
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Choice of Metals
Until 180 nm generation, most wires were aluminum
Modern processes use copper
– Cu atoms diffuse into silicon and damage FETs
– Must be surrounded by a diffusion barrier
Metal
Bulk resistivity (mW*cm)
Silver (Ag)
1.6
Copper (Cu)
1.7
Gold (Au)
2.2
Aluminum (Al)
2.8
Tungsten (W)
5.3
Molybdenum (Mo)
5.3
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Sheet Resistance
Typical sheet resistances in 180 nm process
Layer
Sheet Resistance (W/)
Diffusion (silicided)
3-10
Diffusion (no silicide)
50-200
Polysilicon (silicided)
3-10
Polysilicon (no silicide)
50-400
Metal1
0.08
Metal2
0.05
Metal3
0.05
Metal4
0.03
Metal5
0.02
Metal6
0.02
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Contacts Resistance
Contacts and vias also have 2-20 W
Use many contacts for lower R
– Many small contacts for current crowding around
periphery
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Wire Capacitance
Wire has capacitance per unit length
– To neighbors
– To layers above and below
Ctotal = Ctop + Cbot + 2Cadj
s
w
layer n+1
h2
Ctop
t
h1
layer n
Cbot
Cadj
layer n-1
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Capacitance Trends
Parallel plate equation: C = eA/d
– Wires are not parallel plates, but obey trends
– Increasing area (W, t) increases capacitance
– Increasing distance (s, h) decreases capacitance
Dielectric constant
– e = ke0
e0 = 8.85 x 10-14 F/cm
k = 3.9 for SiO2
Processes are starting to use low-k dielectrics
– k 3 (or less) as dielectrics use air pockets
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M2 Capacitance Data
Typical wires have ~ 0.2 fF/mm
– Compare to 2 fF/mm for gate capacitance
400
300
M1, M3 planes
s = 320
Capacitance decreases
with spacing
250
s = 480
s=
200
8
s = 640
Isolated
s = 320
150
s = 480
s = 640
s=
100
8
C total (aF/ m m)
Capacitance increases
with metal planes
above and below
350
50
0
0
500
1000
1500
2000
w (nm)
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Diffusion & Polysilicon
Diffusion capacitance is very high (about 2 fF/mm)
– Comparable to gate capacitance
– Diffusion also has high resistance
– Avoid using diffusion (and polysilicon) runners for
wires!
Polysilicon has lower C but high R
– Use for transistor gates
– Occasionally for very short wires between gates
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Lumped Element Models
Wires are a distributed system
– Approximate with lumped element models
N segments
R
R/N
C
R/N
C/N
C/N
R
R
C
L-model
C/2
R/N
R/N
C/N
C/N
R/2 R/2
C/2
p-model
C
T-model
3-segment p-model is accurate to 3% in simulation
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RC Example
Metal2 wire in 180 nm process
– 5 mm long
– 0.32 mm wide
Construct a 3-segment p-model
– R = 0.05 W/
=> R = 781 W
– Cpermicron = 0.2 fF/mm
=> C = 1 pF
260 W
260 W
260 W
167 fF 167 fF
167 fF 167 fF
167 fF 167 fF
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Wire RC Delay Example
Estimate the delay of a 10x inverter driving a 2x
inverter at the end of the 5mm wire from the
previous example
– R = 2.5 kW*mm for gates
– Unit inverter: 0.36 mm nMOS, 0.72 mm pMOS
781 W
690 W
– tpd = 1.1 ns
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Driver
500 fF 500 fF
Wire
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4 fF
Load
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Crosstalk
A capacitor does not like to change its voltage
instantaneously
A wire has high capacitance to its neighbor.
– When the neighbor switches from 1→ 0 or 0→ 1,
the wire tends to switch too.
– Called capacitive coupling or crosstalk
Crosstalk effects
– Noise on non switching wires
– Increased delay on switching wires
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Miller Effect
Assume layers above and below on average are quiet
– Second terminal of capacitor can be ignored
– Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
– Miller effect
Delay and power
B
DV
Ceff(A)
MCF
Constant
VDD
Cgnd + Cadj
1
Switching
with A
0
Cgnd
0
Switching
opposite A
2VDD Cgnd + 2 Cadj
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2
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increase
A
C gnd
B
C adj
C gnd
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Crosstalk Noise
Crosstalk causes noise on non switching wires
If victim is floating:
– model as capacitive voltage divider
DVvictim
Cadj
Cgnd-v Cadj
DVaggressor
Aggressor
DVaggressor
Cadj
Victim
Cgnd-v
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DVvictim
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Driven Victims
Usually victim is driven by a gate that fights noise
– Noise depends on relative resistances
– Victim driver is in linear region, agg. in saturation
– If sizes are same, Raggressor = 2-4 x Rvictim
DVvictim
Cadj
1
DVaggressor
Cgnd-v Cadj 1 k
Raggressor
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Cgnd-a
DVaggressor
aggressor Raggressor Cgnd-a Cadj
k
victim
Rvictim Cgnd-v Cadj
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Aggressor
Cadj
Rvictim
Victim
Cgnd-v
DVvictim
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Coupling Waveforms
Simulated coupling for Cadj = Cvictim
Aggressor
1.8
1.5
1.2
Victim (undriven): 50%
0.9
0.6
Victim (half size driver): 16%
Victim (equal size driver): 8%
0.3
Victim (double size driver): 4%
0
0
200
400
600
800
1000
1200
1400
1800
2000
t (ps)
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Noise Implications
So what if we have noise?
If the noise is less than the noise margin, nothing
happens
Static CMOS logic will eventually settle to correct
output even if disturbed by large noise spikes
– But glitches cause extra delay
– Also cause extra power from false transitions
Dynamic logic never recovers from glitches
Memories and other sensitive circuits also can
produce the wrong answer
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Wire Engineering
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Goal: achieve delay, area, power goals with
acceptable noise
Degrees of freedom:
– Width
– Spacing
– Layer
– Shielding
vdd a
0
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a
1
gnd a
2
a
3
vdd
vdd a
0
gnd a1 vdd a
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gnd
a
0
b
0
a
1
b
1
a
2
b
2
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Repeaters
R and C are proportional to l
RC delay is proportional to l2
– Unacceptably great for long wires
Break long wires into N shorter segments
– Drive each one with an inverter or buffer
Wire Length: l
Driver
Receiver
N Segments
Segment
l/N
Driver
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l/N
Repeater
l/N
Repeater
Repeater
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Receiver
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Repeater Design
How many repeaters should we use?
How large should each one be?
Equivalent Circuit
– Wire length l
• Wire Capacitance Cw*l, Resistance Rw*l
– Inverter width W (nMOS = W, pMOS = 2W)
• Gate Capacitance C’*W, Resistance R/W
Rwl/N
R/W
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Cwl/2N Cwl/2N
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C'W
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Showing that repeater insertion pays
w/o repeater k=1
1.21RoCo Ri Ci 0.16 Ri 2Ci 2 0.56 RoCo Ri Ci 0.49 Ro 2Co 2
0 0.16 Ri 2Ci 2 0.65RoCo Ri Ci 0.49 Ro 2Co 2
0 0.4 Ri Ci 0.7 RoCo 0.09 RoCo Ri Ci
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2
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small
33
Under what condition repeater insertion should take place?
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Cascaded driver with non-repeated interconnect
Non-repeated interconnect
The method is useful when Rtr is dominant and Cint is large
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Optimal Buffer Insertion
v
?
?
?
?
?
?
u,q
?
u,q
d v, ui : driver to receiver delay. Root required time: T min qi d v, ui .
i
Buffer reduces load delay but adds internal delay, power and area.
Problem 1:
max
buffer insertions
Problem 2:
max
min q d v, u by buffer insertion at internal nodes.
minq d v,u , s.t. power and area constraints.
buffer insertions
i
i
i
i
i
i
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Delay Model
d v, ui R jiC j R j L j
j
jp i
R4
4
C4
R2
2
R5
C3
0
R1
C5
1
R6
C1
R3
C2
T k - nodes of sub-tree rooted at node k
6
C6
3
p k - nodes along path from root to node k
5
R7
7
C7
Rkl jp k p l R j - resistance along common paths
Lk jT k C j - capacitance of sub-tree
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Bottom-Up Solution
TK min TM , TN
LK LM LN
sub-tree
(TM , LM)
(T’K , L’K)
(TK , LK)
RK
without buffer
1
TK TK RK LK RK CK
2
LK LK CK
RM
M
CM
K
sub-tree
CK
RN
(TN , LN)
N
CN
with buffer
TK TK Dbuffer Rbuffer LK RK Cbuffer
1
RK CK
2
LK Cbuffer CK
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Scaling
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Scaling
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