Transcript Transistors and Layout 1 - University of Western Ontario

Lecture 4
Transistor as Switch
Jan. 13 2003
Modern VLSI Design 3e: Chapter 2
week2-1
Partly from 2002 Prentice Hall PTR
Topics
 Transistor

structures.
Transistor as a switch
Modern VLSI Design 3e: Chapter 2
week2-2
Partly from 2002 Prentice Hall PTR
Transistor structure
n-type transistor:
Modern VLSI Design 3e: Chapter 2
week2-3
Partly from 2002 Prentice Hall PTR
The Nobel Prize in Physics 1956

William Bradford Shockley
– Semiconductor Laboratory of Beckman
Instruments, Inc. Mountain View, CA, USA

John Bardeen
– University of Illinois Urbana, IL, USA

Walter Houser Brattain
– Bell Telephone Laboratories Murray Hill, NJ,
USA
Modern VLSI Design 3e: Chapter 2
week2-4
Partly from 2002 Prentice Hall PTR
N Transistor
Modern VLSI Design 3e: Chapter 2
week2-5
Partly from 2002 Prentice Hall PTR
P Transistor
Modern VLSI Design 3e: Chapter 2
week2-6
Partly from 2002 Prentice Hall PTR
Transistor
Digital: switch
 Analog: many characteristics


Example: inverter
– P transistor + N transistor == one inverter
Modern VLSI Design 3e: Chapter 2
week2-7
Partly from 2002 Prentice Hall PTR
Inverter
+
a
Modern VLSI Design 3e: Chapter 2
out
week2-8
Partly from 2002 Prentice Hall PTR
Inverter layout
VDD
+
a
tub ties
out transistors
a
out
(tubs not
shown)
GND
Modern VLSI Design 3e: Chapter 2
week2-9
Partly from 2002 Prentice Hall PTR
Example 1
+
out
b
Modern VLSI Design 3e: Chapter 2
a
Write the truth
Table of this circuit?
week2-10
Partly from 2002 Prentice Hall PTR
NAND layout
VDD
+
out
b
a
out tub
ties
b
a
GND
Modern VLSI Design 3e: Chapter 2
week2-11
Partly from 2002 Prentice Hall PTR
Example 2
+
Write the truth
Table of this circuit?
b
a
out
Modern VLSI Design 3e: Chapter 2
week2-12
Partly from 2002 Prentice Hall PTR
NOR gate
+
b
a
out
Modern VLSI Design 3e: Chapter 2
week2-13
Partly from 2002 Prentice Hall PTR
NOR layout
b
VDD
a
tub ties
b
out
out
a
GND
Modern VLSI Design 3e: Chapter 2
week2-14
Partly from 2002 Prentice Hall PTR
Difference of digital and analog

Digital: switch
– High level

Analog: characteristics of transistor
– Low level
Modern VLSI Design 3e: Chapter 2
week2-15
Partly from 2002 Prentice Hall PTR
Example 3
Transmission gate:
Modern VLSI Design 3e: Chapter 2
week2-16
Partly from 2002 Prentice Hall PTR
Lecture 5
Transistor Fabrication Process
Jan. 15 2003
Modern VLSI Design 3e: Chapter 2
week2-17
Partly from 2002 Prentice Hall PTR
Topics
 Transistor
 Basic
structure (switch)
fabrication steps.
Modern VLSI Design 3e: Chapter 2
week2-18
Partly from 2002 Prentice Hall PTR
Transistor structure
n-type transistor:
Modern VLSI Design 3e: Chapter 2
week2-19
Partly from 2002 Prentice Hall PTR
Fabrication services

Educational services:
–
–
–
–

U.S.: MOSIS
EC: EuroPractice
Taiwan: CIC
Japan: VDEC
Fab companies: mainly South Asia
Modern VLSI Design 3e: Chapter 2
week2-20
Partly from 2002 Prentice Hall PTR
Fabrication processes

IC built on silicon substrate:
– some structures diffused into substrate;
– other structures built on top of substrate.
Substrate regions are doped with n-type and
p-type impurities. (n+ = heavily doped)
 Wires made of polycrystalline silicon
(poly), multiple layers of aluminum (metal).
 Silicon dioxide (SiO2) is insulator.

Modern VLSI Design 3e: Chapter 2
week2-21
Partly from 2002 Prentice Hall PTR
Simple cross section
SiO2
metal3
metal2
metal1
transistor
via
poly
n+
Modern VLSI Design 3e: Chapter 2
p+
n+
substrate
substrate
week2-22
Partly from 2002 Prentice Hall PTR
What is
N
and P
Substrate
 Poly
 Well (tub)
 Metal
 Via

Modern VLSI Design 3e: Chapter 2
week2-23
Partly from 2002 Prentice Hall PTR
Photolithography
Mask patterns are put on wafer using photosensitive material:
Modern VLSI Design 3e: Chapter 2
week2-24
Partly from 2002 Prentice Hall PTR
Process steps
First place tubs to provide properly-doped
substrate for n-type, p-type transistors:
p-tub
p-tub
substrate
Modern VLSI Design 3e: Chapter 2
week2-25
Partly from 2002 Prentice Hall PTR
Process steps, cont’d.
Pattern polysilicon before diffusion regions:
poly
gate oxide
p-tub
Modern VLSI Design 3e: Chapter 2
poly
p-tub
week2-26
Partly from 2002 Prentice Hall PTR
Process steps, cont’d
Add diffusions, performing self-masking:
poly
n+
p-tub
Modern VLSI Design 3e: Chapter 2
poly
n+
p+
week2-27
p-tub
p+
Partly from 2002 Prentice Hall PTR
Process steps, cont’d
Start adding metal layers:
metal 1
metal 1
vias
poly
n+
p-tub
Modern VLSI Design 3e: Chapter 2
poly
n+
p+
week2-28
p-tub
p+
Partly from 2002 Prentice Hall PTR
Transistor structure
n-type transistor:
Modern VLSI Design 3e: Chapter 2
week2-29
Partly from 2002 Prentice Hall PTR
Question
How many layers?
 Aluminum or copper?
 Technology is P-MOS or N-MOS?
 What is the purpose of silicon?

Modern VLSI Design 3e: Chapter 2
week2-30
Partly from 2002 Prentice Hall PTR
A complete fabrication process
Modern VLSI Design 3e: Chapter 2
week2-31
Partly from 2002 Prentice Hall PTR
Transistor structure (cont’d)
n-type transistor:
Modern VLSI Design 3e: Chapter 2
week2-32
Partly from 2002 Prentice Hall PTR
Questions (cont’d)

Order of Poly !!!
– Self-aligned
What is the carrier for N-transistor and Ptransistor?
 Complete inverter ?

– Need metals and vias
Modern VLSI Design 3e: Chapter 2
week2-33
Partly from 2002 Prentice Hall PTR
0.25 micron transistor (Bell Labs)
gate oxide
silicide
source/drain
poly
Modern VLSI Design 3e: Chapter 2
week2-34
Partly from 2002 Prentice Hall PTR
Review
N transistor
 P transistor

Modern VLSI Design 3e: Chapter 2
week2-35
Partly from 2002 Prentice Hall PTR
Examples
Switch
 Fabrication process

Modern VLSI Design 3e: Chapter 2
week2-36
Partly from 2002 Prentice Hall PTR