Transcript Digital Pixel Image Sensors - Information Systems Laboratory

Trends in CMOS Image Sensor
Technology and Design
Abbas El Gamal
Department of Electrical Engineering
Stanford University
CCD Image Sensors
• High QE and low dark current
• Serial readout:
– Slow readout
– Complex clocking and supply
requirements
– High power consumption
• Cannot integrate circuitry on
chip
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CMOS Image Sensors
• Memory-like readout:
– Enables high speed
operation
– Low power consumption
– Region of interest
Row Decoder
Reset
Word
Word
Pixel
Bit
Column Amplifiers / Caps
Column ADC / Mux
Bit
• Integration
• Enable new applications:
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–
–
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Embedded imaging
High dynamic range
Biometrics
3D imaging
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Image Sensor Market
Thousands of Units
200,000
180,000
CMOS
160,000
140,000
120,000
CCD
100,000
80,000
60,000
40,000
20,000
0
2001
Source: In-Stat/MDR, 8/02
2002
2003 2004
Year
2005
2006
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CMOS Image Sensors Today
• Most sensors:
– application-specific (optical mouse)
– low end (PC, toys)
• Fabricated in old (0.6-0.35mm) processes
– limited integration
• Lower performance than CCDs:
– Not used in digital cameras
– Some exceptions (Canon D30/D60)
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Technology and Design Trends
• Recent developments in:
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–
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Silicon processing
Color Filter Array and Microlens
Miniaturized packaging
Pixel design
Camera-on-chip
• Promise to broaden CMOS image sensor
applicability and enhance their performance
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This Talk
• Silicon processing:
– Sub-micron CMOS process modifications
– Triple-well photodetector
• Applications of modified processes:
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–
–
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Integrated color pixel
Multi-mega pixel sensors
Camera-on-chip integration
Pixel-level ADC – Digital Pixel Sensor
• High Frame Rate Sensors and Applications
– High dynamic range
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Scaling
• CMOS image sensors have benefited from
scaling:
– smaller pixels
– higher fill factor
– greater pixel functionality (PPS  APS)
• Need 0.18mm and below process for
camera-on-chip integration
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Problems with standard CMOS
• Low photoresponsivity -- shallow junctions,
high doping
• High junction leakage -- STI, salicide
• High transistor leakage – off-current, thin
gate oxide
• Poor analog circuit performance
Wong IEDM’96
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Improving Photoresponsivity
Microlens Overcoat
Microlens
Microlens Spacer
Color Filter
Color Filter
Color Filter
Color Filter Planarization Layer
SEM photograph of 3.3mm pixel
Courtesy of TSMC
• Deeper non-silicided
lightly doped diode
junctions (NW/PSUB,
Ndiff/PSUB)
• High transmittance
SiON materials
• Micro-lens and CFA
integration
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Quantum Efficiency
QE of 0.18mm CMOS Photodiode
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0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
450
500
550
600
650
700
750
800
Wavelength (nm)
Courtesy of TSMC/Pixim
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Reducing Leakage
• Junction leakage reduction:
– Non-silicided double-diffused source/drain
implants
– Hydrogen annealing
– Pinned-diode
• Transistor leakage reduction:
– Thick gate oxide transistors
– Thresholds adjusted to increase voltage swing
• Leakages of sub 1nA/cm2 achieved
Wuu, IEDM, 2001
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Drawbacks of Color Filter Array
• Loss of resolution
– aliasing
• Color cross-talk
• Increase microlens to
photodetector distance
• Adds manufacturing
steps and cost
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Triple-Well Photodetector (Foveon)
Column
Out Green
Column
Out Blue
Vcc
Vn
Row Select
Reset
Vcc
Column
Out Red
Vp
Row Select
Reset
Vn
Vcc
Row Select
N Ldd
P Well
N Well
P Substrate
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Triple-well
• Advantages:
– No loss of resolution
– Elimination of photon loss due to CFA
– Elimination of color cross-talk
• Challenges:
– Larger pixel size – less pixels than standard
sensors for same area
– High spectral overlap between three color
channels
– Fabrication and circuit operation ?
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Spectral Response
Relative Response
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Courtesy Foveon, Dick Lyon
0.9
Green
Blue
Red
0.8
Triple-Well
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
450
500
550
600
650
700
600
650
700
1
Courtesy TSMC
0.9
0.8
0.7
CFA
0.6
0.5
0.4
0.3
0.2
0.1
0
400
450
500
550
Wavelength (nm)
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Integrated Color Pixel
Light filters using
patterned metal layers
Catrysse, IEDM, 2001
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Enabling CMOS Technology
Smallest Period in CMOS Technology
0.13 um
400
500
0.18 um
600
700
0.25 um
800
900
1000
Wavelength (nm)
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Integrated Color Pixel
• Using metal patterns above each photodetector,
wavelength selectivity can be controlled
• Needs 0.13um process or multiple layers in 0.18 for
good selectivity in the visible range
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1D ICPs under imaging conditions
0.5
Transmittance
0.45
0.4
0.35
Pixels with
increasing
gap width
0.3
0.25
0.2
0.15
0.1
400
500
600
700
800
Wavelength (nm)
900
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Multiple Layers in 0.18mm CMOS
One layer
Two layers
0.6
Transmittance
0.5
0.4
0.3
0.2
0.1
0
400
500
600
700
800
Wavelength (nm)
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Layer Alignment in 0.18mm CMOS
Two layers (Aligned)
Two layers (Offset)
0.6
Transmittance
0.5
0.4
0.3
0.2
0.1
0
400
500
600
700
800
Wavelength (nm)
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Scaling to 0.13mm CMOS
0.18 mm
0.15 mm
0.13 mm
0.6
Transmittance
0.5
0.18 mm
0.4
0.3
0.13 mm
0.2
0.1
0
400
500
600
700
800
Wavelength (nm)
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Multi-Mega Pixel Sensors
• Memory-like readout of CMOS image
sensors an advantage over CCDs
(Kozlowski, et al, IEDM, 1999)
• Recent examples:
– Kodak DCS Pro 14n (13.7 Megapixels)
– Canon 1Ds (11 Megapixels)
– Foveon 10X (10 Megapixel Triple-Well)
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Camera-on-Chip Integration
Image
Sensor
Memory
Analog
Proc &
ADC
ASIC
PC-Board
Today
Image
Sensor
&
ASIC
ADC
Memory
Camera-on-chip
PC-Board
Future
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Camera-on-chip Applications
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Digital Pixel Sensor (DPS)
ADC
Memory
• Developed at Stanford (under PDC program)
• ADC per pixel and all ADCs operate in parallel
• Advantages:
– Better technology scaling (integration) than APS
– Very high speed digital readout
– No column read noise or Fixed Pattern Noise
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Row Address Decoder
DPS Block Diagram
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Pixel
Block
Sense Amplifiers and Latches
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High Speed DPS Chip
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0.18mm CMOS
352 x 288 pixels (CIF)
9.4mm x 9.4mm pixels
37 transistors/pixel
3.8 million transistors
8 bit single slope ADC
and memory / pixel
• 64 wide digital output
bus at 167 MHz
Kleinfelder, ISSCC, 2001
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Pixel Schematic
Data I/O
Reset V
Reset
PG
Tx
RAMP
Read
Thick-oxide
Sensor
Comparator
8-bit Memory
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ADC Operation
Counter
(Gray Code)
Gray Code
Counter
RAMP
Input
Latched
Value
RAMP
8
+
_
Comp Out
Memory
Input
8
Digital Out
Comp
Out
0
Memory
Loading
1
0
Memory
Latched
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Video Sequence at 10,000 FPS
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Video Sequence at 700 FPS
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High Frame Rate Applications
• High frame rate enables new still and
video imaging applications:
– Dynamic range extension
– Motion blur prevention
– Optical flow estimation
– Motion estimation
– Tracking
– Super-resolution
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Multiple-Capture Single-Image
DSP
• Operate sensor at high frame rate
• Process high frame rate data on-chip
• Output data at standard rates
• Integration of sensor with embedded DRAM and
DSPs enables low cost implementation (Lim‘01)
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HDR via Multiple Capture
T
2T
4T
8T
16T
32T
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HDR Image
• Use Last-Sample-Before-Saturation Algorithm
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HDR Example
Two captures of same high dynamic range scene
Courtesy of Pixim
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DPS HDR Comparison
CCD2
CCD1
DPS
Courtesy of Pixim
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HDR Image via Multiple Capture
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Extending DR at Low Illumination
• For given exposure time, LSBS only extends DR at
high illumination -- Read noise is not reduced
• Increasing exposure time limited by motion blur
Input
Short exposure
Long exposure
• Liu, ICASSP, 2001 describe an algorithm for
extending DR at low illumination and preventing
motion blur
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SNR and DR Enhancement
60
50
Weighted Averaging
Last Sample Before Saturation
Single Capture
SNR (dB)
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DR=47dB
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DR=85dB
20
10
DR=77dB
0
10-1
100
101
iph (fA)
102
103
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65 Image Capture Example
0 ms
10 ms
20 ms
30 ms
40 ms
50 ms
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High Dynamic Range Image
LSBS
Estimation / Motion Prevention
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Integration Beyond Camera-on-chip
DPS
Imaging
Array
Lim, SPIE, 2001
Frame
Memory
SIMD
Processor
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Summary
•
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# Transistors
Transistors Per Pixel
5mm pixel with 30% fill factor
512
256
128
64
32
16
8
4
2
1
0.35
0.25
0.18
0.15
0.13
0.10
0.07
0.05
Technology ( m)
ITRS Roadmap
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Motivation
• PPS/APS do not scale well with technology:
– Analog scaling problems
– Sensitive to digital noise coupling
• Modified 0.18mm CMOS enables camera-on-chip:
– low cost and power consumption
• Digital Pixel Sensor:
– Scales well and less sensitive to digital noise
– Can operate at high frame rate
• Integration + high frame rate can be used to
enhance sensor performance beyond CCDs
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Current Pixel Architectures
• Passive Pixel (PPS):
– Small pixel, large fill factor
– Slow readout, low SNR
– Reading is destructive
• Active Pixel (APS):
– Larger pixel, lower fill factor
– Faster readout, higher SNR
– Most popular architecture
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Micro-lens and CFA Integration
Microlens Overcoat
Microlens
Microlens Spacer
Color Filter
Color Filter
Color Filter
Color Filter Planarization Layer
SEM photograph of 3.3mm pixel
Courtesy of TSMC
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