Transcript Lecture Note3

Memory & IO
Interfacing to CPU
Lec note 3
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 1
outline
 Z80 Minimal Configuration
 Z80 Memory connection
 Address Bit Map
 Memory Map
 Full and Partial Decoding
 1 Bit Memory With Separated I/O
 Z80 Input Output
 Simplified Drawing of 8088 Minimum Mode
 8088 Memory connection
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 2
Minimal Configuration of a
Z80 Microcomputer
Clock
Generator
Memory
(ROM, RAM)
Power
Supply
Address Bus
Z - 80 CPU
Input
Output
(I/O)
Data Bus
Control Bus
hsabaghianb @ kashanu.ac.ir
Microprocessors
Out
In
3- 3
Z80 Memory connection
CPU 16 bit address bus  64 k memory(max)
CPU 8 bit data bus  8 bit data width
Generally should be connected
Data to data
Address to address
Wr to wr
Rd to rd
Mreq to cs
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 4
Memory connection (cont.)
 If only one RAM chip Full size (64 kb capacity)
D7~D0
D7~D0
RAM
64 kb
A15~A0
A15~A0
RD
Z80
CPU
WR CS
RD
WR
MREQ
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 5
Memory connection (cont.)
 If RAM capacity was 32 kb
 A15 composed with MREQ
 RAM area is from 0000h to 7FFFh
D7~D0
D7~D0
RAM
32 kb
A14~A0
A14~A0
RD
Z80
CPU
WR CS
RD
WR
A15
hsabaghianb @ kashanu.ac.ir
MREQ
Microprocessors
3- 6
Memory connection (cont.)
 There is two 32 kb RAM
 Problem: Bus Conflict. The two memory chips will
provide data at the same time when
microprocessor performs a memory read.
 Solution: Use address line A15 as an “arbiter”. If
A15 outputs a logic “1” the upper memory is
enabled (and the lower memory is disabled) and
vice-versa.
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 7
Memory connection (cont.)
 There is two 32 kb RAM
 A15 applied to select one RAM chip
 Two RAM area is from 0000h to 7FFFh (RAM1)
and 8000h to FFFFh (RAM1)
D7~D0
D7~D0
RAM
32 kb
A14~A0
A14~A0
RD
Z80
CPU
WR CS
D7~D0
RAM
32 kb
A14~A0
RD
WR CS
RD
WR
A15
hsabaghianb @ kashanu.ac.ir
MREQ
Microprocessors
3- 8
Memory connection (cont.)
 32 kb ROM and 32 kb RAM
 ROM doesn’t have wr signal
D7~D0
D7~D0
ROM
32 kb
A14~A0
A14~A0
OE
Z80
CPU
D7~D0
RAM
32 kb
A14~A0
CS
RD
WR CS
RD
WR
A15
hsabaghianb @ kashanu.ac.ir
MREQ
Microprocessors
3- 9
Memory connection (cont.)
There is 4 memory chip
A14 and A15 applied to chip selection
D7~D0
A13~A0
Z80
CPU
D7~D0
ROM
16 kb
A13~A0
CS
OE
D7~D0
D7~D0
D7~D0
RAM
RAM
RAM
16 kb
16 kb
16 kb
A13~A0
A13~A0
A13~A0
RD
WR CS
RD
WR CS
RD
WR CS
RD
WR
A14
A15
MREQ
En
S0
S1
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 10
Address Bit Map
Selects chip
Selects location within chips
A15 to A0
(HEX)
AA AA
11 11
54 32
AAAA
1198
10
AAAA
7654
AAAA
3210
0000h
00 00
0000
0000
0000
3FFFh
00 11
1111
1111
1111
4000h
01 00
0000
0000
0000
7FFFh
01 11
1111
1111
1111
8000h
10 00
0000
0000
0000
BFFFh
10 11
1111
1111
1111
C000h
11 00
0000
0000
0000
FFFFh
11 11
1111
1111
1111
hsabaghianb @ kashanu.ac.ir
Microprocessors
Memory
Chip
ROM
RAM1
RAM2
RAM3
3- 11
Memory Map
 Represents the memory type
0000h
 Address area of each memory chip
 Empty area
D7~D0
4000h
D7~D0
D7~D0
ROM
16 kb
A13~A0
A13~A0
D7~D0
RAM
16 kb
A13~A0
CS
OE
RD
WR CS
7FFFh
D7~D0
RAM
16 kb
RAM
16 kb
A13~A0
RD
WR CS
8000h
A13~A0
RD
WR CS
RD
WR
A14
A15
MREQ
3FFFh
BFFFh
C000h
En
S0
S1
hsabaghianb @ kashanu.ac.ir
FFFFh
Microprocessors
ROM
16k
RAM1
16k
RAM2
16k
RAM3
16k
3- 12
Memory Map
 Empty Area cann’t write and read
0000h
 Read op. returns FFh value (usualy)
ROM
3FFFh
 Write op. cann’t store any value on it
4000h
Empty
D7~D0
D7~D0
D7~D0
ROM
16 kb
A13~A0
A13~A0
RAM
16 kb
RAM
16 kb
A13~A0
CS
OE
7FFFh
D7~D0
RD
WR CS
A13~A0
RD
WR CS
RD
WR
A14
A15
MREQ
8000h
BFFFh
C000h
En
S0
S1
hsabaghianb @ kashanu.ac.ir
RAM2
RAM3
FFFFh
Microprocessors
3- 13
Memory Map
 Empty Area cann’t write and read
 Read op. returns FFh value (usualy)
 Write op. cann’t store any value on it
0000h
ROM
3FFFh
4000h
Empty
D7~D0
D7~D0
ROM
16 kb
A13~A0
7FFFh
D7~D0
A13~A0
RD
WR CS
RD
WR
A14
A15
MREQ
8000h
A13~A0
CS
OE
RAM
16 kb
RAM
BFFFh
C000h
En
Empty
S0
S1
hsabaghianb @ kashanu.ac.ir
FFFFh
Microprocessors
3- 14
Full and Partial Decoding
 Full (exhaust) Decoding
 All of the address lines are connected to any memory/device
to perform selection
 Absolute address : any memory location has one address
 Partial Decoding
 When some of the address lines are connected the
memory/device to perform selection
 Using this type of decoding results into roll-over addresses
(fold back or shading).
 roll-over address : any memory location has more than one
address
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 15
Partial Decoding
 A15~A12 has no connection
 Then doesn’t play any role in addressing
 What is the Memory and Address Bit map?
D7~D0
D7~D0
RAM
4 kb
A11~A0
A11~A0
A15~A12
Z80
CPU
X
RD
WR CS
RD
WR
MREQ
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 16
Partial Decoding
0000h
0FFFh
1000h
 Every memory location has more than one address
 For example first RAM location has addresses:
0000h
1000h
2000h
3000h
Roll-over Address
1FFFh
2000h
2FFFh
3000h
3FFFh
…………….
…………….
F000h
FFFFh
F000h
D7~D0
A15 to A0
(HEX)
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
X000h
xxxx
0000
0000
0000
XFFFh
xxxx
1111
1111
1111
hsabaghianb @ kashanu.ac.ir
AAAA
3210
Memory
Chip
RAM
Microprocessors
RAM
RAM’
RAM’
RAM’
RAM’
D7~D0
RAM
4 kb
A11~A0
A11~A0
A15~A12
Z80
CPU
X
RD
WR CS
RD
WR
MREQ
3- 17
Partial Decoding
 A12 only connected to RAM
 A13 has no connection
 What is the memory map?
D7~D0
D7~D0
ROM
4 kb
A12~A0
A13
Z80
CPU
A15
A14
hsabaghianb @ kashanu.ac.ir
A11~A0
X
OE
D7~D0
RAM
8 kb
A12~A0
CS
RD
WR CS
RD
WR
MREQ
Microprocessors
3- 18
Partial Decoding
 8 roll-over address for ROM
 4 roll-over address for RAM
D7~D0
D7~D0
D7~D0
ROM
4 kb
A11~A0
A12~A0
Z80 A13
CPU
X
OE
RD
WR
A15
A14
MREQ
hsabaghianb @ kashanu.ac.ir
RAM
8 kb
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210
0xxx
0000
0000
0000
0xxx
1111
1111
1111
X0x0
0000
0000
0000
X0x1
1111
1111
1111
Memory
Chip
A12~A0
CS
RD WR CS
Microprocessors
ROM
RAM
3- 19
Partial Decoding
0000h
0000h
RAM’
1FFFh
D7~D0
ROM
4 kb
A11~A0
A12~A0
Z80 A13
CPU
X
OE
RAM
8 kb
A12~A0
CS
2000h
RAM’
D7~D0
Conflict
1000h
1FFFh
2000h
D7~D0
0FFFh
3FFFh
2FFFh
3000h
3FFFh
4000h
4000h
4FFFh
RD WR CS
5000h
5FFFh
5FFFh
A15
A14
RD
WR
6000h
6000h
MREQ
7FFFh
7000h
7FFFh
8000h
F000h
6FFFh
ROM
ROM’
ROM’
ROM’
ROM’
ROM’
ROM’
ROM’
RAM
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
0xxx
0000
0000
AAAA
3210
Memory
Chip
9FFFh
A000h
RAM’
0000
0xxx
1111
1111
1111
X0x0
0000
0000
0000
X0x1
1111
1111
1111
hsabaghianb @ kashanu.ac.ir
4k
BFFFh
ROM
C000h
8k
RAM
DFFFh
E000h
FFFFh
Microprocessors
FFFFh
3- 20
Partial Decoding
0000h
0000h
0FFFh
1000h
1FFFh
1FFFh
2000h
2000h
2FFFh
D7~D0
D7~D0
D7~D0
ROM
4 kb
A11~A0
A12~A0
Z80 A13
CPU
X
OE
RAM
8 kb
RD WR CS
5FFFh
6000h
A15
A14
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210
0xxx
0000
0000
0000
0xxx
1111
1111
1111
X1x0
0000
0000
0000
1111
Memory
Chip
4k
ROM
5000h
Conflict
6000h
6FFFh
7FFFh
7000h
7FFFh
8000h
F000h
ROM’
ROM’
ROM’
ROM’
ROM’
ROM’
ROM’
9FFFh
A000h
BFFFh
C000h
RAM
8k
DFFFh
RAM
E000h
1111
RAM’
FFFFh
hsabaghianb @ kashanu.ac.ir
4FFFh
5FFFh
RAM’
MREQ
1111
4000h
RAM’
RD
WR
X1x1
3FFFh
4000h
A12~A0
CS
3000h
3FFFh
ROM
Microprocessors
FFFFh
3- 21
Full (exhaustive) decoding
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210
0000
0000
0000
0000
0001
1111
1111
1111
0010
0000
0000
0000
0010
0111
1111
1111
Memory
Chip
A12~A0
ROM
A12~A0
D7~D0
2764
EPROM
8k8
RAM
OE
CE
D7~D0
C
Y0
A12
B
Y1
0800h-0FFFh
A11
A
Y2
1000h-17FFh
74138
Y3
1800h-1FFFh
7421
A10~A0
2000h-27FFh
A10~A0
D7~D0
A15
G2A
Y5
6116
RWM
2k8
A14
G2B
Y6
RD WR CS
G1
Y7
Y4
MREQ
RD
0000h-07FFh
A13
RD WR
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 22
Partial decoding
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210
0000
0000
0000
0000
0001
1111
1111
1111
001x
x000
0000
0000
001x
x111
1111
1111
Memory
Chip
A12~A0
ROM
A12~A0
D7~D0
2764
EPROM
8k8
RAM
OE
CE
D7~D0
A15
C
Y0
A14
B
Y1
A13
A
Y2
74138
RD
0000h-1FFFh
2000h-3FFFh
A10~A0
Y3
A10~A0
D7~D0
MREQ
G2A
Y5
6116
RWM
2k8
GND
G2B
Y6
RD WR CS
VCC
G1
Y7
Y4
RD WR
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 23
1 Bit Memory With Separated I/O
D7-D0
D7
D1
Din
A11-A0
A11~A0
Dout
2147
RWM
4k1
WR / RD CS
D0
Din
Din
A11-A0
A11~A0
Dout
2147
RWM
4k1
WR / RD CS
A11~A0
A11-A0
Dout
2147
RWM
4k1
WR / RD CS
WR / RD
CS
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 24
What is the memory(addr. bit) map
A12~A0
D7~D0
2764
EPROM
8k8
OE
A15
C
Y0
A14
B
Y1
A13
A
Y2
74138
RD
0000h-1FFFh
2000h-3FFFh
D7-D0
MREQ
G2A
Y5
GND
G2B
Y6
VCC
G1
Y7
WR
RD
hsabaghianb @ kashanu.ac.ir
D7
A11-A0
A11~A0 Dout
2147
RWM
4k1
WR / RD CS
D0
D1
Din
Y3
Y4
CE
Din
Din
A11-A0
A11~A0 Dout
2147
RWM
4k1
WR / RD CS
A11-A0
A11~A0 Dout
2147
RWM
4k1
WR / RD CS
WR
Microprocessors
3- 25
Adding RAM & ROM
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 26
Minimum Z80 Computer System
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 27
Z80-µP-Family (Typical Environment)
PIO
DMA
+5V
INT -
INT -
IEI
RDY
System Buses (Address, Data, Control)
INT -
INT -
Z80 CPU
INT -
CTC
+5V
IEI
W/RDYB -
SIO
IEO
ZC/TO1 ZC/TO2
hsabaghianb @ kashanu.ac.ir
IEO
Microprocessors
IEI
TxCA TxCB RxCA RxCB -
3- 28
Z80 Input Output
 Z80 at most could have 256 input port and 256 output
 8 bit port address is placed on A7–A0 pin to select the
I/O device
 OUT (n), A
 n is 8 bit port address
 Content of A is data
 OUT (C), r
 Content of C is a port address
 r is a data register
 IN A, (n)
 n is 8 bit port address
 Data is transfered to A
 IN r (C)
 Content of Reg C is a port address
 Input data is transfered to r (data reg)
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 29
Remember IO read/write cycle
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 30
Z80 and simple output port
A15
A14
:
A0
Z80
CPU
D7
D6
D5
D4
D3
D2
D1
D0
OUT (03), A
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
74LS373 Q4
D5
Q5
D6
Q6
D7
Q7
LE
OE
WR
IORQ
IOWR
hsabaghianb @ kashanu.ac.ir
AAA A AAAA
765 4 3210
Microprocessors
3- 31
Z80 and simple input port
A15
A14
:
A0
Z80
CPU
D7
D6
D5
D4
D3
D2
D1
D0
IN A, (02)
5V
Y0
A0
Y1
A1
Y2
A2
Y3
A3
Y4 74LS244 A4
Y5
A5
Y6
A6
Y7
A7
G1 G2
RD
IORQ
IORD
hsabaghianb @ kashanu.ac.ir
AAAA AA AA
7654 32 10
Microprocessors
3- 32
8088 and simple output port
A19
A18
:
A0
8088
Minimum
Mode
D7
D6
D5
D4
D3
D2
D1
D0
D0
Q0
D1
Q1
D2
Q2
D3
Q3
D4
74LS373 Q4
D5
Q5
D6
Q6
D7
Q7
LE
OE
IOR
IOW
AAAAAAAAAAAAAAAAIOW
1 111119 87654 3210
5 43210
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 33
8088 and simple input port
A19
A18
:
A0
What is this?
8088
Minimum
Mode
D7
D6
D5
D4
D3
D2
D1
D0
5V
Y0
A0
Y1
A1
Y2
A2
Y3
A3
Y4 74LS244 A4
Y5
A5
Y6
A6
Y7
A7
G1 G2
IOR
IOW
AAAAAAAAAAAAAAAAIOW
1 111119 87654 3210
5 43210
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 34
Simplified Drawing of 8088 Minimum Mode
A7 - A0
DEN
DT/R
E
DIR
GND
A15 - A8
GND
OE
LE
A7-A0
Q7 - Q0
A15-A8
74LS373
D7 - D4
D3 - D0
A19/S6-A16/S3
ALE
OE
LE
Q7 - Q0
74LS373
D7 - D0
GND
8088
OE
LE
D7-D0
74LS245
D7 - D0
AD7 - AD0
B7 - B0
Q7 - Q4
Q3 - Q0
A19-A16
74LS373
MEMR
RD
IO / M
MEMW
WR
IOR
IOW
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 35
Minimum Mode
220 bytes or 1MB memory
D7 - D0
D7 - D0
A19 - A0
A19 - A0
Simplified
Drawing of
8088 Minimum
Mode
1 MB
Memory
MEMR
RD
MEMW
WR
CS
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 36
Memory location
What is the memory location of a 1MB (220 bytes)
Memory?
A19 to
A0
(HEX)
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210
00000
0000
0000
0000
0000
0000
FFFFF
1111
1111
1111
1111
1111
Example: 34FD0
0011 0100 11111 1101 0000
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 37
Minimum Mode
512 kB memory
D7 - D0
A19
D7 - D0
What do we do with A19?
A18 - A0
Simplified
Drawing of
8088 Minimum
Mode
A18 - A0
1)
2)
Don’t connect it
Connect to cs
512 kB
Memory
What is the difference?
MEMR
RD
MEMW
WR
CS
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 38
512 kB Memory Map
 Don’t connect it


00000h
A19 is not connected to
the memory so even if
the 8088 microprocessor
outputs a logic “1”,the
memory cannot “see” it.
A19=0 is the same as
A19=1 for Memory
 Connect to cs

7FFFFh
80000h
FFFFFh
00000h
If A19=0 Memory chip
act normal fanction
7FFFFh
512k
Mem
512k
Mem’
512k
Mem
80000h
FFFFFh
hsabaghianb @ kashanu.ac.ir
Microprocessors
Empty
3- 39
2  512 kB memory
D7 - D0
D7 - D0
512 kB
RAM1
A19
A18 - A0
A18 - A0
RD
WR
MEMR
MEMW
Simplified
Drawing of
8088 Minimum
Mode
CS
D7 - D0
512 kB
RAM2
A18 - A0
hsabaghianb @ kashanu.ac.ir
MEMR
RD
MEMW
WR
Microprocessors
CS
3- 40
2512 kB memory
What are the memory locations of
two consecutive 512KB (219 bytes)
Memory?
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210
0000
0000
0000
0000
0000
0111
1111
1111
1111
1111
1000
0000
0000
0000
0000
1111
1111
1111
1111
1111
Memory
Chip
00000h
512k
RAM1
7FFFFh
80000h
ROM
512k
RAM2
RAM
FFFFFh
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 41
Interfacing four 256K
Memory Chips to
8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
CS
A17
A17
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
:
A0
D7
:
D0
RD
WR
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#1
CS
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 42
Interfacing four 256K
Memory Chips to
8088 Microprocessor
A17
:
A0
D7
:
D0
RD
WR
A19
A18
CS
A17
A17
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
256KB
#4
:
A0
D7
:
D0
RD
WR
256KB
#3
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#2
CS
A17
:
A0
D7
:
D0
RD
WR
256KB
#1
CS
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 43
Memory chip#__ is mapped to:
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210
Memory
Chip
RAM#1
RAM#2
RAM#3
RAM#4
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 44
A12
Interfacing
several 8K
Memory
Chips to
8088 P
:
A19
A18
A17
A16
A15
A14
A13
A0
D7
:
D0
RD
WR
8KB
#?
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 45
A12
Interfacing
128
8K Memory
Chips to
8088 P
:
A19
A18
A17
A16
A15
A14
A13
A0
D7
:
D0
RD
WR
8KB
#128
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 46
A12
Interfacing
128
8K Memory
Chips to
8088 P
:
A0
D7
A19
A18
A17
A16
A15
A14
A13
:
D0
RD
WR
8KB
#128
CS
A12
:
:
:
A0
D7
:
D0
MEMR
MEMW
8088
Minimum
Mode
A12
:
A0
D7
:
D0
RD
WR
8KB
#2
CS
A12
:
A0
D7
:
D0
RD
WR
8KB
#1
CS
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 47
Memory chip#__ is mapped to:
AAAA
1111
9876
AAAA
1111
5432
AAAA
1198
10
AAAA
7654
AAAA
3210
Memory
Chip
RAM#1
RAM#2
RAM#126
RAM#127
RAM#128
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 48
Memory map & Address Bit map
A12~A0
A12~A0
D7~D0
2764
EPROM
8k8
OE
7408
A14
C
Y0
A13
B
Y1
A12
A
Y2
74138
A10~A0
Y4
MREQ
G2A
A15
G2B
Y6
VCC
G1
Y7
A10~A0
D7~D0
6116
RWM
2k8
RD WR CS
RD
hsabaghianb @ kashanu.ac.ir
D7~D0
RD
Y3
Y5
CE
Microprocessors
74244 input
G1G2
WR
3- 49
8255
Programmable Peripheral Interface (PPI)
Has 3 8_bit ports A, B and C
Port C can be used as two 4 bit ports CL and Ch
Two address lines A0, A1 and a Chip select CS
8255 can be configured by writing a control-word
in CR register
hsabaghianb @ kashanu.ac.ir
Microprocessors
3- 50
Interfacing with 8255
A2
C
Y0
A3
B
Y1
A4
A
Y2
74138
/CS
8255
Y3
Y4
A0
A1
IOEQ
G2A
Y5
A5
G2B
Y6
A6
G1
Y7
D7-D0
/WR
/RD
hsabaghianb @ kashanu.ac.ir
Microprocessors
A0
A1
D7-D0
/RD
/WR
3- 51