Transcript Miller capability effect

IGBT driving aspect
Zhou Yizheng
IGBT driving
 Driving voltage level
 Effect of turn on/off
¬ Rge, Cge, Lg
¬ Driving capability
 Isolation
 Thermal
 Protection
¬ Parasitic turn on
¬ Over voltage
¬ Short circuit/over current
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Driving voltage level
Tvj=125C
 Positive voltage
Effect to Vcesat
Vge，Vcesat
note：max. allowed Vge is
20V
Effect to short cicuit
Vge，Isc（tsc）
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Tvj=125C
Driving voltage level
 Negative voltage
¬ To guarantee safety off
state, avoid parasitic
miller turn on
¬ Turn on delay increase
(dead time)
¬ Slightly reduce tf and
Eoff
Miller capability effect
¬ Increase driving power
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Effect of turn on/off
 Rgon
Control of dv/dt and di/dt with gate resistor
Turn-on with smaller than
nominal gate resistor:
Turn-on with nominal gate
resistor (datasheet value):
Turn-on with larger than nominal
gate resistor:
dv/dt = 1.4kV/µs
di/dt = 8.7kA/µs
ICpeak = 2.7kA
Eon = 544mWs
dv/dt = 0.9kV/µs
di/dt = 6.4kA/µs
ICpeak = 2.4kA
Eon = 816mWs
dv/dt = 0.3kV/µs
di/dt = 3.0kA/µs
ICpeak = 1.8kA
Eon = 2558mWs
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Effect of turn on/off
 Rgoff
Control of dv/dt and di/dt with gate resistor
•dv/dt is controllable with gate resistor. A larger resistor will result in a smaller dv/dt.
•di/dt is only controllable if the gate voltage doesn’t drop below the Miller Plateau level before IC starts
to decrease. This is in general the case for a gate resistor value close to the datasheet value. With
larger resistors a control of di/dt starts to work.
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Effect of turn on/off
 Cge
Independently control of dv/dt and di/dt
Range Determined by Condition Influenced by
Influence on
1
VGE < VGEth
Ciss = const
RG, CGE
tdon
2
VGEth < VGE < VGEM
Ciss = const
RG, CGE
di/
dt
3
VGE = VGEM
VGE = const
RG, CGC
dv/
dt
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For similar Eon, we can:
Rge
Cge
Eon
Di/dt
Ipeak
tdon
Vge_p
4.6ohm
0nf
650mJ
3283kA/
us
1.487kA
1.76us
13.6V
1.7ohm
200nf
635mJ
2492kA/
us
1.386kA
1.67us
13.7V
1.7ohm200nF
4.6ohm0nF
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For similar di/dt, we can:
Rge
Cge
Eon
Di/dt
Ipeak
tdon
Vge_p
2.6ohm
0nf
437mJ
4270kA/
us
1.639kA
1.29us
14.0V
1.7ohm
46nf
386mJ
4324kA/
us
1.635kA
1.23us
15.0V
1.7ohm46nF
2.6ohm0nF
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Rge vs. Cge
 Using Cge shows better Eon*di/dt coefficient
 Using Cge can significantly increase driving power
P=∆U*(Qge+Cge*∆U)*f
 Using Cge can significantly increase driving peak current, require
more powerful driver (output peak current capability)
 The tolerance of Cge should be taken care when used in IGBT
paralleling application
 Using Cge may cause gate current oscillation, which leads to
higher gate peak voltage.
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Cable length influence
With long cable
With short cable
Calbe
Rge
Short
Long
Cge
Eon
Di/dt
0.9ohm 0nf
196mJ
0.9ohm 0nf
87mJ
Ipeak
tdon
Vge_p
6128kA 1.978k
/us
A
0.92us
14.7V
6920kA 2.220k
/us
A
0.92us
18.3V
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For similar Eon, we can:
 With fixed Cge
Calbe
Rge
Short
Long
Cge
Eon
Di/dt
0.9ohm 22nf
210mJ
1.7ohm 22nf
Ipeak
tdon
Vge_p
5882kA 1.908k
/us
A
0.92us
17.0V
231mJ
5587kA 1.874k
/us
A
1.21us
17.5V
Eon
Di/dt
tdon
Vge_p
 With fixed Rge
Calbe
Rge
Cge
Ipeak
Short
1.7ohm 22nf
351mJ
4717kA 1.711k
/us
A
1.17us
15.8V
Long
1.7ohm 91nf
347mJ
4065kA 1.673k
/us
A
1.39us
15.6V
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Cable length influence
 Cable length (Lg) shows similar Eon*di/dt coefficient as Rge,
This mainly due to Lg effect both during di/dt period and dv/dt
period (same as Rge)
 Long cable significantly induce the turn on delay time
 Long cable is a EMI receiver, which can cause Vge spike and
unstable.
 Loosing gate cable inductance will significantly increase Eon,
which should especially paid attention in active adaptor design.
Adaptor board
Rge
Cge
Eon
Di/dt
Ipeak
Active
1.0ohm
0nf
332mJ
5650kA/us
1.708kA
Passive(8mm)
1.0ohm
0nf
187mJ
7700kA/us
1.895kA
Long cable should be avoid to be used. But loosing gate inductance
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2009. All rights
reserved.
should
alsoTechnologies
be paid
attention
Effect of turn on/off
 Driving capability
¬ Peak current capability
 Maximum driver peak current
I Gmax 
ΔU

R G(min)
Slow down turn on/off speed
ΔU
Driver losses
R G extern  R G intern
U = 30V @ 15V switching
¬ Power capability
 Driver power
P tot  PDriver  PGate
Vge goes down
PGate  f  Q  ΔU
or
PGate  f  3...5  C iss  ΔU
Power supply losses
2
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Effect of turn on/off
 Turn on/off criteria
Redundant information on di/dt and dv/dt
3
2
2000
2000
IR(t) [A]
Diode SOA
V R [5 0 0 V/ d i v ] IR [ 5 0 0 A/ d i v ]
3000
1000
!
!
1
1000
0
0
locus iR(t)*vR(t)
2
1000
0
2000
0
1
0
ti me [4 00ns/ di v]
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1000
2000
VR(t) [V]
3
3000
Isolation
+
Optocoupler
 High isolation capability
Optical Fiber
 Aging of electrical
characteristic
 Reduced reliability due to
aging
 No energy transmission
Monolithic
Level Shifter
 Cost effective
 No galvanic isolation
 Integration of logic suitable
 EMI sensitivity
 No energy transmission
Discrete
Transformer
 Very high isolation
Capability
 Energy transmission
possible
Coreless
Transformer (CLT)
 High isolation capability
 Expensive
 Device Volume
 No energy transmission
 Very cost effective
 Easy integration of logic
function
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Isolation
 Isolation transformer
¬ Isolation test
¬ Partial discharge test
¬ Parasitic capacitor (Primary - secondary)
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Thermal
 Influenced parameters
 Module case temperature
 Driving power (switching frequency, Qg)
 Driving peak current
 Sensitive parts
 Gate resistor
 Booster
 Power supply
 Fiber
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Thermal
 If system internal ambient temperature is known.
 From delt Tca, we can check temperature rise due to module
itself heating
 Adding temperature rise due to driving signal, real driver board
temperature can be gotten.
Pg
T
Tc
Rth_1
System cooling can significant
improve driver cooling condition
Rth_2
Ta
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Protection
 UVLO
 Interlock / generating deadtime
 Vge over voltage
 Parasitic turn on
 Short circuit protection
 Over voltage protection (for short circuit off)
¬ Active Clamping
¬ DVRC (Dynamik Voltage Raise Control)
¬ di/dt-Feedback
¬ Soft-Shut-Down
¬ Two-Level Turn-off
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Protection
 UVLO
¬ Avoid driving IGBT with low voltage causing thermal issue
¬ Avoid series break down
 Interlock / generating deadtime
¬ Avoid short through by software mistake
¬ Hardware deadtime should be shorter than software deadtime
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Protection
 Vge over voltage
¬ Limitation of increase of gate voltage due to positive feedback over CGC
and due to di/dt
¬ Limitation of short circuit currents
Methode 1
Gate-Supply Clamping
Methode 2
Gate-Emitter Clamping
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Protection
 Parasitic turn on
¬ minus voltage off
¬ separate gate resistors, using small Rgoff and big Rgon
¬ Additional gate emitter capacitor to shunt the Miller current
¬ Active Miller clamping
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Protection
 Short circuit protection
 Desaturation detect
Vce
Ic
Vce
Ic
SC I
OC
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SC II
Protection
 Short circuit protection
 Desaturation detect
Based on fixed reference voltage
Based on variable reference voltage
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Protection
 Short circuit protection
 Desaturation detect
 Over current protection?
– Noise immunity is poor
– Blanking time hard to set for fixed reference voltage concept, especially
for high voltage module
– Current protect point hard to be accurate
¬ Directly detect collector current
¬ Digital controller to detect di/dt
¬ By system current sensor
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Protection
 Over voltage protection
¬ Active clamping
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Protection
 Over voltage protection
¬ DVRC (Dynamic Voltage Raise Control)
uGE(t)
iC(t)
UF4007
100
pF
dic/dt=11kA/µs
@ Tj=25°C
3xSM6T220A
IRFD 120
47R
UF4007
UAC
4xSM6T220A
+16
V
uCE(t)
RG=3.6W
EOFF=0.9J
BYD77
RMO
S
56
ZPD16
44H
11
MFP-D
PWM
15R
BYD77
MFN-D
45H
11
URAC
RAC=15
W
RG=1.5
W
FZ2400R17KE3
uGE(t)
iC(t)
dic/dt=3.4kA/µs
@ Tj=25°C
-16V
uCE(t)
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RG=13W
EOFF=1.95J
Protection
 Over voltage protection
¬ di/dt protection
Gate boost
Detect &
comparison
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Protection
 Over voltage protection
¬ Soft shut down
Rg
Rssd
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Protection
 Over voltage protection
¬ Two level turn off
Driver Out
IC
VGE
Driver Out
VCE
Without Two-Level Turn-Off
VCE reaches 1000V
IC
VGE
VCE
With Two-Level Turn-Off
VCE reduced to 640V
Copyright © Infineon Technologies 2009. All rights reserved.