Transcript poster

MV5: A RECONFIGURABLE SIMULATOR FOR
HETEROGENEOUS MULTICORE ARCHITECTURES
Simulators for Today’s Architectures
Jiayuan Meng*, Kevin Skadron
University of Virginia
* Now at Argonne National Laboratory
Do you need it?
Single-Instruction, Multiple-Threads
If you want to explore:
Out-of-Order (OO) core: SimpleScalar
So what is MV5?
Simultaneous Multithreading: SMTSIM
Chip-multiprocessor w/t OO cores: SESC
Break it,
Use it!
SIMD + IO/OO
SIMD + coherent caches
SIMD + OCN
Simple Banked Cache
Underlying
middleware
GPU-like SIMD (SIMT)
Chip-multiprocessor w/t In-Order (IO), OO
cores: Simics+Gems+Garnet, SimFlex
Hardware thread scheduler
API for SIMD threads
If you are OK with
Intel’s Microarchitecture: PTLSim
Directory-based coherence
(MESI, MSI)
GPU: GPGPUSim
Simulation Management
for space exploration
General purpose / Heterogeneous / Integrated Accelerators?
Diversity
Modularity
Scalability
Co-design
B
C
A / 11111111
B / 11111001
Post-dominator
C / 00000110
D / 11111111
time
(a) The example program
(b) Branch divergence
and re-convergence
System emulation
Kernels
M5 provides such a platform
MV5 is based on M5
Separate basic cache
functionalities with
coherence protocols
Potential Configurations
Core
Core
L1 Cache
L1 Cache
BlkState
BlkState
MESI/MSI
DirState
L2 Cache
SIMD
OO
DRAM
On-chip Network
In-order
D
On-chip Network
(Mesh)
But Future is Unpredictable…
•
•
•
•
A
MV5 Website
caches
https://sites.google.com/site/mv5sim/home
DRAM
MV5 Mailing list:
http://groups.google.com/group/mv5sim
Acknowledgements
This work was supported in part by SRC grant No. 1607, NSF grant nos. IIS-0612049
and CNS-0615277, a grant from Intel Research, and a professor partnership award from
NVIDIA Research. We would like to thank Jeremy W. Sheaffer, David Tarjan, Shuai
Che, and Jiawei Huang for their helpful inputs in power modeling, area estimation, and
benchmark implementations.
Dual Core
Tiled Cores
OO+SIMD
Note: SIMD cores can share the same address space
with other cores over coherent caches!