Transcript slides

ISCA 2005 panel on
Chip multiprocessors are here.
But, where are the threads?
Babak Falsafi
Computer Architecture Lab (CALCM)
Carnegie Mellon
© 2005 Babak Falsafi
End of Single Thread Era?
MIPS
1000000
100000
10000
1000
Multiple cores
Multithreaded
cores
OoO
Superscalar
100
10
First RISC
1
Cores
0.1
0.01
1970
1980
1990
• Good news: 1 TIPS by 2010
• Bad news: where is the “I” in TIPS?
2000
2010
2
1. Hand program them?
40-years, still not mainstream
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Limited to skilled folks
Need to think parallel at all stack levels
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Algorithms, languages, systems, etc.
Not your typical undergrad curriculum
Decomposition first, PRAM, or dataflow?
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Is Transactional Memory the right solution to the
wrong problem?
Is this an architecture problem?
3
2. Automatically parallelize?
Parallelizing compilers/languages:
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30-year effort, modest results
Works for data-parallel
Thread-Level Speculation:
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15-year effort, less than modest results
Less than 10% speedup with 4 cores
Hand tuning helps but doesn’t solve the
problem
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3. Use them for helpers/nannies?
Performance:
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Precomputation, slipstream, microthreading,…
E.g., better memory, branch performance
Similar success/failure as TLS
Functionality:
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Garbage collection, reliability, security
How many nannies does a program need?
Is this an effective use of real-estate?
5
Our Distinguished Panel
Mr. Transaction
Mr. Impact
Mr. Stampede
Michael
Wolfe
Mr. Multiscalar
Mr. Niagara
Mr. Supercompiler
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