Transcript ppt

ECE465 Lecture Notes # 11
Clocking Methodologies
Shantanu Dutt
UIC
Acknowledgement: (1) Most slides prepared by Huan Ren from Prof. Dutt’s Lecture
Notes (some modifications made by Prof. Dutt). (2) Some slides extracted from
Prof. David Pan’s (UT Austin) slides as indicated.
Timing Methodologies
• Synchronous Sequential Circuits
External I/P
External O/P
Comb.
Logic
00,11/0
TOPP,Logic
Memory
(critical path delay
In the o/p logic part)
TNSP,Logic
(critical path delay
In the NS logic part)
Clk
• Features Required for Correct
Operation
– 1) All State Transitions take place
only with respect to a particular
event in the clock (e.g., positive
or negative edge, etc. )
01/1
00,01,10/0 B
01/0
11/0
11/0
C
10,00/1
A
Transition occurs only on
positive edge of Clk
Timing Methodologies (contd)
• Features Required for Correct Operation
– 2) Only one state transition should take place in one clock period.
– 3) All inputs to all FFs/latches should be correctly available with
appropriate setup time (Tsetup or Tsu) and hold time (Thold or Th)
around the triggering edge of the clock.
≥ Tsetup
≥ Thold
Input
Clock
Tperiod
=TClk
i’th state
transition
(i+1)’th state (i+2)’th state
transition
transition
[could be to
the same state]
(i+3)’th state
transition
Clock Routing
• A path from the clock source to clock sinks (FFs)
• Different FFs are at different distances from the clock source
Clock Source
FF
FF
FF
FF
FF
FF
FF
FF
FF
FF
• This leads to the clock arriving at different FFs at slightly different time.
This difference in clock arrival times is called clock skew
From: David Pan, UT Austin
Timing Methodologies: Clock Skew Problem
Real-world problems that can cause the three requirements to be violated:
A)Clock Skew: Max(arrival time difference of the “same” clock edge betw all FF
pairs): can cause hold time or setup time violations.
1.
Hold time violation problem:
Safe: If blue horse wins race & wins it by a margin of at least Th
2
1
Unsafe: If brown horse wins race
1
IN
1
D1
Clk
0 1
D Q
FF1 Q1
Clk1
Logic
0
D2
0
D Q
FF2 Q2
2 Values before
the clock +ve
Clk2
edge
Clk1
Clk2
New value of D2
D1
Current
overwrites old value
state
00
10
before Q2 changes D2
Correct
Incorrect
transition
transition
This causes an incorrect Q1
11
Q2 change when +ve
Q2
edge arrives at Clk2
Tskew
Safe Value of Tskew
IN 1
•Tskew= max (|difference between
clock pulses (rising edges) of clock
D1
inputs of any two FFs in the system|)
≥Tsu
≥Th
Clk
Clk1
D1
Typical or
min TPLH
Q1
min TP,Logic
D2
•
Clk2
Tskew
≥Th
0
D Q
FF1 Q1
Clk1
Logic
0
D2
0
D Q
FF2 Q2
Clk2
Safe if: min (TPLH of FF)+min (TP,Logic
between Q1 & Q2)>Tskew+Th
i.e. if: Tskew < min (TPLH)+min (TP,Logic) -Th
Similarly for 1 to 0 transition of Q1: TPHL
comes into play, then safe if: Tskew < min
(TPHL)+min (TP,Logic)-Th
Thus we need:
Tskew < min (min TPLH, min TPHL)+min (TNSP,Logic) –Th
= min(TP,FF) + min(TNS P,Logic) – Th,
where TNSP,Logic is the prop. delay of the next state (NS)
logic portion of the entire comb. logic in the system,
which is the relevant logic block wrt clock skew
• Thus, the safe Tskew limit is based on minimum
propagation delay of FFs and the NS logic
Another problem of clock skew
2. Clock skew causes another problem: Startup time violation
– If the clock is not designed taking skew into account, then there will not be enough
time to complete the FF-load and comb. logic operations Tsu time before the next
clock edge arrives at Clk2
– If clock skew is taken into account, as it should be, the clock period Tclk will be larger
by an amount of Tskew, thus making it “unnecessarily” slower
Less time avail. for
logic and FF delays
TFF + Tlogic + Tsu
Tskew
Clk2
0
D Q
FF1 Q1
Clk1
Tclk
Clk1
IN 1
D1
Logic
0
D2
0
D Q
FF2 Q2
Clk2
Clk
Determining Clock Period: Edge Triggered
System
Level sens.
latch
TOPP,Logic
Comb.
Logic
Positive
edge trigg.
Clk
FF1
negative
edge trigg.
Clk
Clk1 FF2
Clk2
Tsu T
skew
TP,FF TP,Logic
Clk1
Clk2
TNSP,Logic
Memory of FF bank
with delay TP,FF
Clk
Max(typical TPHLand typical TPLH)
TClk-Tskew > max(TP,FF)+ max(TNSP,Logic)+Tsetup
= TP,FF+ TNSP,Logic+Tsetup
TClk
i.e., we will use the normal convention of using
• TP,FF to mean max(TP,FF)
• TNSP,Logic to mean max(TNSP,Logic)
Also, TClk-Tskew > TP,FF+ TOPP,Logic, where TOPP,Logic
is the output logic portion of combinational logic.
Determining the Clock Period (Contd.)
≥ TP,FF + TNSP,Logic + Tsetup, AND
≥ TP,FF + TOPP,Logic
Clk1
• If with skew
TClk
– TClk> Tskew+ TP,FF+ TNSP,Logic +Tsetup AND
– TClk> Tskew+ TP,FF+ TOPP,Logic
– Thus TClk> max(Tskew+ TP,FF+ TNSP,Logic +Tsetup, Tskew+ TP,FF+ TOPP,Logic)
• Use 10% buffer for safety
– TClk=1.1max(Tskew+ TP,FF+ TNSP,Logic +Tsetup, Tskew+ TP,FF+ TOPP,Logic)
• Tskew= max (|difference between clock pulses (rising edges) of clock inputs
of any two FFs in the system|)
Determining the Clock Period of a Datapath w/ a Controller FSM
• Ignoring clock skew here for simplicity. Can be added later on after deciding the
non-skew clock period by adding 1.1Tskew to it.
Registers
Datapath
FFs
n
Output
Logic
n
Delay1 = TP,FF
+ TNSP,Logic +Tsetup
I/Ps (external + from datapath)
Next State
Comb.
m1
Logic
Control logic
(muxes, decoders,
tri-state buffers, load/enablei/ps)
CLK
O/Ps (= Control Signals)
m2
Delay2 = TP,FF+ T
T1=max(Delay1, Delay2)
What if the smallest subpath delay Dmin is > T1. Why
waste resources counting ceiling(Dmin/T1) cc’s?
A simple technique: Find the approximate greatest
common divisor (gcd) of the various subpath delays.
Update T1=max(Delay1, Delay2, above gcd).
This reduces time wastage due to a slack between
end of a subpath delay and the next clock +ve edge,
and also reduces counting overhead compared to if
we had set T1=max(Delay1, Delay2, Dmin), since the
gcd of all subpath delays Di’s <= Dmin
Make TClk = 1.1T1
Each subpath w/ delay Di will then have cc delay of
ceiling(Di/ TClk)
op
P,Logic
+max(Tcontrol_logic)
Subpath delay Di =
TP,FF+ TFU(s) + Tsetup
(TopP,Logic + Tmux &/or
Tdemux if mux &/or demux
on the subpath)
FU(s)
FU(s)
FU(s)
B) Another Problem in Seq. Circuits: Race
Condition (multiple state changes in a cc)
• A race condition occurs when a FF/latch output changes more than
once in a clock cycle (cc).
• This happens when after the O/P of a latch changes, it feeds back to its
input via some logic when the latch is still enabled in the same cc. This
cause the O/P to change again.
≥Tsu
Other I/Ps
Clk
Comb.
Logic
D
Q
D latch
Q
Clk
2 changes of state in Q in 1 cc
D
Race Condition (contd)
• Race condition is generally a problem with level sensitive latches.
• Can be solved using:
Other I/Ps
– a) Edge-triggered FFs.
Comb.
Clk
Logic
Q
D
D FF
D
Clk
Q
Only 1 O/P change per cc.
– b) Narrow-width clocking.
TClk
T >T
+T
Other I/Ps
TP,Logic+Tsetup
Tw < min (TP,FF)+min(TP,Logic)
Clk
Tw
skew
Comb.
Logic
P,FF+
min (min TPLH, min TPHL)
Q
D latch
D
Narrow
Width Clk
Correct State Transition Using Level-Sensitive
Latches: No race cond. but potential exists
0/1
0/0
Transition for the darkened arrow:
1
Comb.
Logic
1
1
CS
2 level
sens.
latches
0
0
Clk
00
0
1/1
1/0
1
NS
10
Comb.
Logic
1
0
0
1
Clk
0
1/1
0/1
1
1/0
0/0
01
Comb.
Logic
0
0
1
1
Clk
01
0
Race Condition due to unequal path delays for different NS bits:
Incorrect State Transition Using Level-Sensitive Latches
0/1
Required transition for the thick
arrow becomes incorrect transition
corresponding to the dashed arrow
1
0
Comb.
Logic
1
1 slow
Comb.
Logic
1
1
0
1
1 fast
Comb.
Logic
1
1
0
Clk
1
Clk
Clk
1
1
0
0
2 level-sens. latches
0/0
10
00
1/1
1/0
0
1
Comb.
Logic
1
0
1
0
Clk
1
1/1
0/1
1
1/0
01
0/0
Comb.
Logic
0
0
0
0
Clk
11
1
No Race Condition Using Edge-Triggered FFs
0/1
0/0
• Correct transition for the darkened
arrow irrespective of the relative speed
of different excitation (next state) outputs
1
0
Comb.
Logic
1
1 slow
Comb.
Logic
1
1
0
0
1 fast
Comb.
Logic
1
1
0
Clk
1
Clk
Clk
1
1
0
00
1/1
1/0
1/1
0/1
0
1
10
Comb.
Logic
1
0
0
1
Clk
1/0
01
01
0/0
0
1
Comb.
Logic
0
0
0 2 M-S or edge- Period Between State
1
triggered FFs Transitions (also clock period) Clk
1
0
No Race Condition Using 2-phase clocking and MS level
0/1
sensitive latches
0/0
• Generally, Cost(master-slave (MS) LS latches) <
Cost(edge-trigg. FF)
00
• Correct transition for the darkened arrow irrespective
of the relative speed of different excitation (next state)
outputs
1
0
1
0
Comb.
Logic
1/1
1/0
1/0
01
1
0
Comb.
Logic
10
0/0
1
0
Comb.
Logic
Comb.
Logic
1
1
1
1
slow
1
0
slow
0
0
0
0
0
0
1 fast
0
1fast
1
1
1
Clk2 Clk1
Clk2 Clk1
Clk2
Clk1 T2-1
Tgap T1-2
Clk2 Clk1
OR
01
Clk2 Clk1
Two-phase clock period determination
I/Ps
Comb.
Logic
CS
TClk
O/Ps
Clk2
aT1-2
NS
Clk1
Clk2 Clk1
(1-a)T1-2
T2-1
Tgap2
Tgap1 T1-2
Tgap1 > Tskew (to avoid overlap and thus a race condition & this also takes care of the skew
problem that reduces that part of clock period available for the delays of the FF + logic + Tsu )
T2-1+aT1-2 (0< a <1) + Tgap1 > TP,FF+TP,Logic+Tsu + Tskew (1)
(Note: Introducing a Tgap1 of at least Tskew also takes care of the reqmt to allow for Tskew in the above sum of
the 3 delay components)
(1- a)T1-2 > TP,FF + Tsu (2)
The value of a is really not going to matter, since disappears in aT1-2 + (1- a)T1-2 = T1-2, and
on adding (1) and (2) we get: T2-1+T1-2 > 2TP,FF+TP,Logic+2Tsu (3)
T1-2 = T2-1 (for symmetry requirements)
Tgap1 = Tgap2 (for symmetry requirements) > Tskew
 this again takes care also of skew reducing the clock period in the various prop. delays and
setup times are incurred. So, finally:
Tclk = 1.1(T2-1 + T1-2 + Tgap1 + Tgap2 ) = 1.1(2TP,FF+TP,Logic+2Tsu+2Tskew) [w/ 10% safety gap]
Note: Tgap1 = Tgap2 = Tskew, takes care of both requirements: a) no overlap in Clk1 and Clk2 due to skew;
b) enough clock period Tclk to process all delays, where two different arrival times of clk1 (or clk2) at two
different master (or slave) latches can differ by Tskew (the "usual" problem that we saw for edge-triggered
FFs). No extra Tskew allowance needed in Tclk for the latter issue.
Clock Skew
• Clock skew is the maximum difference in the arrival time of a clock
signal at two different components.
• Clock skew forces designers to use a large time period between
clock pulses. This makes the system slower.
• So, in addition to other objectives, clock skew should be
minimized during clock routing.
From: David Pan, UT Austin
Clock Design Problem
• What are the main concerns for clock design?
• Skew
– No. 1 concern for clock networks
– For increased clock frequency, skew may
contribute over 10% of the system cycle time
• Power
– very important, as clock is a major power
consumer!
– It switches at every clock cycle!
• Noise
– Clock is often a very strong aggressor
– May need shielding
• Delay
– Not really important
– But slew rate is important (sharp transition)
From: David Pan, UT Austin
The Clock Routing Problem
• Given a source and n sinks (FFs).
• Connect all sinks to the source by an
interconnect tree so as to minimize:
– Clock Skew = maxi,j |ti - tj|
– Delay = maxi ti
– Total wirelength
– Noise and coupling effect
From: David Pan, UT Austin
H-Tree Clock Routing
Tapping Point
4 Points
16 Points
From: David Pan, UT Austin
Method of Means and Medians (MMM)
• Applicable when the clock terminals are arbitrarily
arranged.
• Follows a strategy very similar to H-Tree.
• Recursively partition the terminals into two sets of
equal size (median). Then, connect the center of
mass of the whole circuit to the centers of mass of
the two sub-circuits (mean).
• Clock skew is only minimized heuristically. The
resulting tree may not have zero-skew.
From: David Pan, UT Austin
An Example of MMM
centers of mass
From: David Pan, UT Austin