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Design 4: Edu32 Processor
read=0/1
Memory System
write=0/1
Data Bus (DB)
pc_ab_enb=0/1
4
ir_sel =0/1
PC
IR
pc_enb
=0/1
pc_sel=WB/INC
+
24
16
16->32 ext. x_enb
=0/1
(INC)
.
32
C.U.
FSM
ready
mar_enb
=0/1
MAR
mar_sel=0/1
y_enb=0/1
mdr_db_enb=0/1
MDR
mdr_enb
=0/1
r0_write=0/1
Register
r15_write=0/1 File
source & dest reg addr
(ri, rj, rk)
rega_sel =0/1
Status signals (m31, cout, ovfl)
alu_sel=ADD, ADDA, SUB, etc.
Note: _sel signals to registers are used to
load them; some _sel signals are more than 1 bit
signals when multiple i/ps are coming into the reg.
as in the PC and the MDR. This does not apply to
the register file where the _sel signals have somewhat
different meanings as explained in class.
op_sel =0/1
ALU
mdr_sel
=WB/DB
ri_sel=0/1
rj_sel=0/1
rk_sel=0/1
a_sel=0-15
b_sel=0-15
regb_sel =0/1
O/P Reg.
op_enb
=0/1
Write Bus
24->32 ext.
Address Bus (AB)