Transcript pptx

Safe and Efficient
Supervised Memory Systems
1) Out-of-band metadata per data block
2) Monitor, control (supervise) data accesses
3) Run handlers on specific metadata states
Jayaram Bobba†, Marc Lupon‡,
Mark D. Hill, and David A. Wood
Department of Computer Sciences
University of Wisconsin-Madison
†Intel
†‡
Corporation
‡Universitat
Politècnica
de Catalunya
Work done while at University of Wisconsin-Madison
Why Supervised Memory Systems?
HW more powerful
SW more complex
Productivity Wall
Hardware Support to Improve Productivity
Empty/full-bits
Hardware TM
MemTracker,SafeMem,iWatcher
Deterministic Shared Memory
Supervised (Memory)
Systems
Hardware-assisted GC
Information Flow Tracking
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Executive Summary
• Many supervised memory systems
• Assume SC, but few systems do SC
1. Moving to TSO (x86 & SPARC) non-trivial
2. Supervised Memory for TSO
– TSOall: TSO for data & metadata slow
– TSOdata: TSO for data & metadata tricky
3. Safe Supervision
– Metadata for X only controls data at X
– Fast & Simple
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Outline
• Introduction
• Move To TSO non-trivial
– Case Study: Deterministic Multiprocessor (DMP)
• Supervised Memory for TSO
• Safe Supervision
• Evaluation
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Reordering can be incorrect
A TSO-compliant system
P2
PC
r1
r2
r3
ST 0x01, A
PC
r1
r2
r3
0x01
0x10
ST 1, [A]
LD [B], r1
ST
0x10, C
ST 2,[C]
LD [C], r3
ST A
LD B
Memory
Store
Buffer
Processor
P1
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Block
Data
A
0x00
B
0x01
C
0x11
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Metadata
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Reordering can be incorrect
DMP-ShTab [Devietti et al., ASPLOS 09]
Processor
P1
PC
r1
r2
r3
0x11
0x00
LD [X], r1
LD [B], r2
ST 1, [B]
T1
Memory
STALL
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P2
PC
r1
r2
r3
LD [Y], r2
ST r2, [Y]
ST 2,[A]
LD [B], r3
0xff
0x01
STALL
Block
Data
A
0x10
Owned@T2
Shared@T1,T2
B
0x01
0x00
Shared@T1,T2
Owned@T1
Owned@T2
X
0x11
Owned@T1
Y
0xff
Owned@T2
Private
Shared
T2
Metadata
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ExploreReordering
relaxed supervised
systems
can be incorrect
Memory
Store
Buffer
Processor
Is reordering safe? A Case Study
DMP-ShTab
on
TSO
P1
P2
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PC
r1
r2
r3
0x11
LD [X], r1
LD [B], r2
ST 1, [B]
T1
STALL
PC
r1
r2
r3
LD [Y], r2
ST r2, [Y]
ST
0x10, A
ST 2,[A]
LD [B], r3
0xff
0x00
STALL
Block
Data
Metadata
A
0x10
Shared@T1,T2
B
0x00
Owned@T2
X
0x11
Owned@T1
Y
0xff
Owned@T2
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Private
Shared
T2
Case1: LD B does not pass ST A
r3 gets 0x01
Case2: LD B passes ST A
r3 gets 0x00
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Outline
• Introduction
• Move To TSO non-trivial
• Supervised Memory for TSO
– Define Supervised Memory
– TSOall: Simple but Slow
– TSOdata: Fast but tricky
• Safe Supervision
• Evaluation
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Define Supervised
Memory
Supervised
Memory
for TSO
Supervised Memory
• Each memory location A,
– data (A.d)
– metadata (A.m)
• New operations
– Supervised Load (sLD A)
– Supervised Store (sST A)
• Jump on reading special metadata (Optionally)
– Hardware exception
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Define Supervised
Memory
Supervised
Memory
for TSO
Supervised Operations
sLD A =>
Start:
atomic{
curm = Val[RA.m]
nextm = NEXT(Load, curm)
// Read metadata
// Check software// specified FSM
If nextm == EXCEPTION then
Jump to Handler
If (nextm != curm) then
WA.m,nextm
// Update metadata
RA.d
// Read data
}
Handler:
…
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Supervised Memory for TSO
TSO Axioms
[Hangal et al., ISCA 2004]
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Supervised Memory for TSO
TSO Axioms
[Hangal et al., ISCA 2004]
Axiom
Description
Order
Total Order on all write accesses
Atomicity
No intervening accesses for atomic operations
Termination
All write accesses eventually complete
Value
Reads return latest value from memory or store buffer
Memory
Barrier
No reordering across a barrier
ReadAny
Accesses cannot pass outstanding reads
WriteWrite
Write access cannot pass outstanding writes
Rd A
Rd B
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Rd A
Wr B
Wr A
Wr B
Wr A
Rd B
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Reordering Axioms
Allows store buffers
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Supervised Memory for TSO
TSOall: A Consistency Model for
Supervised Memory
TSO axioms applied to all accesses—data and
metadata
+ (Simple) Like TSO
— (Slow) Prohibits optimizations
Thread: sST A->[Rd A.m, Wr A.d, Wr A.m]
sLD B ->[Rd B.m, Rd B.d]
=> Store buffers ineffective
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Supervised Memory for TSO
Axiom
Description
Order
Total Order on all write accesses
Atomicity
No intervening accesses for atomic operations
Termination
All write accesses eventually complete
Value
Reads return latest value from memory or store buffer
Memory
Barrier
No reordering across a barrier
ReadAny
Data accesses cannot pass outstanding data reads
WriteWrite
Data writes cannot pass outstanding data writes
Reordering Axioms
TSOdata: Fast Yet Simple
Thread: sST B->[Rd A.m, Wr A.d, Wr A.m] Store buffers can
be used
sLDA ->[Rd B.m, Rd B.d]
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Outline
•
•
•
•
•
Introduction
Move To TSO non-trivial
Supervised Memory for TSO
Safe Supervision
Evaluation
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Safe Supervision
Safe Supervision
Motivation
No Reordering, Easy to Reason (TSOall)
vs
Reorder, Performance (TSOdata)
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Safe Supervision
Blast from the Past
[Adve and Hill, ISCA1990]
No Reordering, Easy to Reason (SC)
vs
Reorder, Performance (RC)
• Observation:
– Simple programs rely only on certain SC orders
– Ignore non-essential orders. Still appears as SC
• Challenge: Simple? Non-essential orders?
• Solution: Data-race-freedom
– For data-race-free programs, RC = SC
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Safe Supervision
Safe Supervision
Motivation
No Reordering, Easy to Reason (TSOall)
vs
Reorder, Performance (TSOdata)
• Observation:
– Simple supervised programs rely only on certain orders
– Ignore non-essential orders. Still appears as TSOall
• Challenge: Simple? Non-essential orders?
• Solution: Safe Supervision
– For safely-supervised programs, TSOdata = TSOall
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Safe Supervision
Safe Supervision
• A location’s metadata is only used to control
access to that location’s data
Initially, A.mdata = Empty, B.data = 0
Thread 1:
Thread 2:
B.data = 1
While (A.mdata == Empty);
A.mdata = Full Read B.data
• Most uses of supervision are safely supervised. E.g.,
• Heap Checker: Initialized/Uninitialized values
• Transactional Memory: Conflict Detection information
• DMP is NOT safely-supervised
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Outline
•
•
•
•
•
Introduction
Move To TSO non-trivial
Supervised Memory for TSO
Safe Supervision
Evaluation
– Is reordering useful?
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Reordering is useful
Supervised Systems
• TokenTM [bobba et al., ISCA2008]
– Transactional Memory
– Metadata for tracking read/write-sets
• HARD [zhou et al., HPCA2007]
– Race Detection
– Metadata for tracking sharing state and locksets
• Both safely-supervised
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Reordering is useful
Evaluation Setup
• Systems
– TokenTM on in-order
• TokenTMall on TSOall, TokenTMdata on TSOdata
– HARD on OOO superscalar
• HARDall on TSOall, HARDdata on TSOdata
• Simulation built on Multifacet GEMS
• Workloads
– TokenTM: STAMP
– HARD: Wisconsin Commercial Workload Suite
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Reordering is useful
Performance normalized to
TokenTM_all
Results
TokenTM
1.4
1.2
TokenTM_all
1
TokenTM_data
0.8
Speedups: 3% in Kmeans to 22% in Labyrinth
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Reordering is useful
Results
HARD
Performance normalized to
HARD_all
1.4
1.2
HARD_all
HARD_data
1
0.8
Apache
JBB
OLTP
ZEUS
Speedups: 3% in JBB to 5% in Apache
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In the paper…
• Formal models
– Formal Definition of Safe Supervision
– Proofs (in thesis)
http://www.cs.wisc.edu/multifacet/theses/jayaram_bobba
_phd.pdf
• OpenSPARC case study
– How to handle reordering issues?
– Metadata overhead
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Executive Summary
• Many supervised memory systems
• Assume SC, but few systems do SC
1. Moving to TSO (x86 & SPARC) non-trivial
2. Supervised Memory for TSO
– TSOall: TSO for data & metadata slow
– TSOdata: TSO for data & metadata tricky
3. Safe Supervision
– Metadata for X only controls data at X
– Fast & Simple
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Wisconsin Multifacet Project
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Explore relaxed supervised systems
Deterministic Shared Memory (DMP)
[Devietti et al., ASPLOS 2009]
“depending upon the consistency model of the
underlying hardware, threads must perform a
memory fence at the edge of a quantum”
• Insert a fence after the last operation in the
quantum
• Insert a fence before the first shared operation in
the quantum
I3: Reordered metabit-reads
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Illustration
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Explore relaxed supervised systems
LD
ST
LD
Exception
None
LD/ST
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Memory
Full
Empty
PC
PC
r1
r2
r3
r1
r2
r3
ST 0x01, A
0x01
Store
Buffer
ST
Processor
Is reordering trivial?
Empty/full-bits
ST 1, [A]
LD [B], r1
ST
0x10, C
ST 2,[C]
LD [C], r3
I2: NO LOAD
BYPASS
Block
Data
Metadata
A
0x00
Full
B
0x01
None
C
0x11
Empty
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EXCEPTION
I3: LATE
EXCEPTIONS
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TSOdata on OpenSPARC T2
• Goal: Explore low-level issues on a real design
• Late Exceptions with deferred handlers
– Dump store buffer entries on exception
– Enhance store buffer to carry Virtual Address (VA)
– ~200 cycles to read out 4 entries
• Disable store buffer bypassing for supervised
loads
• Low space overhead for adding metabits (~4%)
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Explore relaxed memory systems
Existing proposals assume SC
• Assume SC or don’t deal with multiprocessors
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Proposal
Base
Architecture
Implementation
WWT
MIPS
SC
Tapeworm
MIPS
SC
LogTM
SPARC
SC
OneTM
SPARC
SC
Informing Memory MIPS, Alpha
SC
SafeMem
x86
x86
MemTracker
MIPS
SC
DMP
x86
SC
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Non-TSOall Executions
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TSOdata is Complex
Empty/full-bits
sST
Empty
sLD
Exception
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Full
Initial State:
A.d = 0, A.m = None
B.d = 0, B.m = Empty
sST
T0:
dST 1, A
sLD B
T1:
sST B, 1
dLD A
Can dLD A return 0?
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Safe Supervision
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