Transcript ppt

ESE370:
Circuit-Level
Modeling, Design, and Optimization
for Digital Systems
Day 20: October 17, 2014
Ratioed Logic
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Penn ESE370 Fall2014 -- DeHon
Previously
• Restoration and Noise Margins
• CMOS Gates
– Drive rail-to-rail
– Only one transistor turned on in steady
state
• Only subthreshold current in steady state
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Today
• Ratioed Gates
– Break all the rules… (nice properties)
• Not rail-to-rail, steady-state-current…
– Correctness
– Performance
– Power
– Implications
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Note on what about to see
• Not clear win
• Should be able to analyze
– Chance to exercise analysis
– Kind of thing you want to be able to
analyze
• Pattern should recognize
• Stepping stone to more interesting
things to come…
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Idea
• Building both pull-up
and pull-down can
be expensive –
many gates
• Seems wasteful to
build logic function
twice
– Once in pullup, once
in pulldown
– Large capacitance
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Idea
• Maybe only need to
build one
• Build NFET
pulldown
– Exploit high N
mobility
• traditional
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Ratioed Inverter
• Does this work?
– Vout for Vin=0V ?
– Vout for Vin=1V ?
WP=1
WN=
1
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Penn ESE370 Fall2014 -- DeHon
Ratioed Inverter
• Does this work?
– Vout for Vin=0V ?
– Vout for Vin=1V ?
WP=1
WN=
1
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Ratioed Inverter Wn=1
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Ratioed Equations
• PMOS roughly fixed current (resistance)
– VGS pinned at –Vdd
ISD 

pCOX W 
2
  VGS VT 
 L 
2

• NMOS current dependent on Vin
– Voltage controlled resistance
IDS 

n COX W 
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  VGS  VT 
 L 
2

n=2p
Wp=Wn=1
Rp=?
Rp=Rp0=2R0
Rn @ Vin=Vdd=?
Rn @ Vin=Vdd/2=?
Only at Vin=Vdd
Does Rn=Rn0=R0
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Ratioed Inverter
• How do we need to size N to
make it work?
WP=1
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DC Transfer Function
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Penn ESE370 Fall2014 -- DeHon
Ratioed Inverter
• How do we need to size P to
make it work?
WN=1
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P vs. N
• Conclude: still prefer N to P for ratioed
logic
– ….at least for now
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Worst-Case Output Drive
Strength?
• Rdrive?
WP=1
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Noise Margin Tradeoff
• What is impact of increasing (reducing)
noise margin?
– On size
– On input capacitance
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Ratioed Inverter Sizing
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Ratioed Inverter Sizing
• What causes knee in curve at high end?
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S
Non-VSAT Equations
IDS 

IDS

n COX W 
2
  VGS  VT 
 L 
2

2 
W 
VDS
 nCOX  VGS VT VDS 

 L 
2 
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Penn ESE370 Fall2014 -- DeHon
D
S
D
Non-VSAT Equations
• P looks roughly like current source
• Must Match current with N
– Determine Vds
– How does Wn effect Vds?
IDS 
IDS

n COX W 
2
  VGS  VT 
 L 
2
2 
W 
VDS
 nCOX  VGS VT VDS 

 L
2 
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Penn ESE370 Fall2014 -- DeHon

S
D
Non-VSAT Equations
• Isdp constant = Idsn
• Once drop into linear region
– Vds < Vgs-Vt
– Constant = (Vgs-Vt) Vds
– Vds α 1/ (Vgs-Vt)
IDS
IDS 

n COX W 
2
  VGS  VT 
 L 
2
2 
W 
VDS
 nCOX  VGS VT VDS 


 L 
2 
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
Size for R0/2 drive?
• How do we size for R0/2 drive?
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Compare Static CMOS
For Rdrive=R0/2 inverter
• Total Transistor Width?
• Input capacitance load?
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Power?
• Istatic ?
• Output high?
– Ileak
• Output low?
– Ipmos_on
– Vdd/(R0/2) -- for our sample case
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Power
• Ptot ≈ a(½Cload+Csc)V2f
+PlowV2/Rpon
+(1-Plow)VI’s(W/L)e-Vt/(nkT/q)
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How size for R0/2 drive?
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How size for R0/2 drive?
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How size for R0/2 drive?
• How size K-input nor?
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When better than CMOS nor-k?
• Better = smaller, lower input capacitance
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Which Implementation is
faster in ratioed logic?
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Illustrates
• Preferred gate changes
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Penn ESE370 Fall2014 -- DeHon
Ideas
• There are other logic disciplines
• We have the tools to analyze
• Ratioed Logic
– Tradeoff noise margin for
• Reduced area? Capacitive load?
– Dissipates static power in one mode
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Admin
• Project
– Should have read it
– Build and simulated baseline over
weekend
– Start list of optimizations to try
• If don’t have list talk with Ron or André during
office hours
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