Transcript ppt
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 20: October 25, 2010 Pass Transistors Synchronous Circuits 1 Penn ESE370 Fall2010 -- DeHon Today • Pass Transistor Logic – Power – Tristates • Clocking – Latches – Registers – Timing discipline 2 Penn ESE370 Fall2010 -- DeHon Pass Transistor Circuits 3 Penn ESE370 Fall2010 -- DeHon Power Implications • What’s the power impact of partial swing? 4 Penn ESE370 Fall2010 -- DeHon Back to Rail • How make it go to rail? 5 Penn ESE370 Fall2010 -- DeHon Transmission Gate 6 Penn ESE370 Fall2010 -- DeHon Level Restorer 7 Penn ESE370 Fall2010 -- DeHon Level Restorer 8 Penn ESE370 Fall2010 -- DeHon Level Restore • What issue arises here? 9 Penn ESE370 Fall2010 -- DeHon Level Restore • What issue arises here? 10 Penn ESE370 Fall2010 -- DeHon Tristate • Sometimes want to be able to not drive a line – Bus driven from different places – I/O port – sometimes read, sometime write 11 Penn ESE370 Fall2010 -- DeHon Tristate Driver 12 Penn ESE370 Fall2010 -- DeHon Tri-State Drivers Clocking Latches, Registers 14 Penn ESE370 Fall2010 -- DeHon Why Clocked Circuits? • Synchronize external events • Reuse logic – FSM – Pipelining • Synchronize internal use of logic 15 Penn ESE370 Fall2010 -- DeHon Challenge • Logic paths have different delays – E.g. different output bits in an adder • Delay of signal data dependent – E.g. length of carry • Delay is chip dependent – E.g. Threshold Variation • Delay is environment dependent – E.g. Temperature 16 Penn ESE370 Fall2010 -- DeHon Challenge • • • • • Logic paths have different delays Delay of signal data dependent Delay is chip dependent Delay is environment dependent Proper behavior depends on inputs being coordinated – Match the inputs that should interact 17 Penn ESE370 Fall2010 -- DeHon Discipline • Add circuit elements to – hold values – and change at coordinated point • Control when changes seen by circuit • Only have to make sure to wait long enough for all results • Decouple – timing of signal change – from timing of signal usage Penn ESE370 Fall2010 -- DeHon 18 Synchronous Discipline • Add state elements (registers, latches) • Compute – From state elements – Through combinational logic – To new values for state elements 19 Penn ESE370 Fall2010 -- DeHon What does this do? 20 Penn ESE370 Fall2010 -- DeHon Latch f=0 Out=In f=1 Out=Out f transitions 01 Out holds value 21 Penn ESE370 Fall2010 -- DeHon Latch • In pass-through mode (f=0), – acts like buffer • In latch mode (f=1), – holds last value given 22 Penn ESE370 Fall2010 -- DeHon Latch • In pass-through mode (f=0), – acts like buffer • In latch mode (f=1), – holds last value given • Timing Requirements? 23 Penn ESE370 Fall2010 -- DeHon Latch Timing • Must present input value sufficiently before the f transitions 01 – Must have time to propagate and charge Out • Setup Time (tsu) – must setup latch input prior to passhold transition 24 Penn ESE370 Fall2010 -- DeHon Latch Timing • Must not change input before switched over to hold state – Takes time for inverter to charge before hold path enabled. 25 Penn ESE370 Fall2010 -- DeHon Latch Timing • Must not change input before switched over to hold state • Hold Time (thold)– must hold data input until passhold transition complete 26 Penn ESE370 Fall2010 -- DeHon What happens here? 27 Penn ESE370 Fall2010 -- DeHon Observe • Latch alone – In flow-through mode half of cycle – Can still get flow-through, combinational cycles 28 Penn ESE370 Fall2010 -- DeHon Multiple Latch Discipline • Open latches at disjoint times • At all times one latch on every path is closed 29 Penn ESE370 Fall2010 -- DeHon Register • Two back-to-back latches – Open one latch at a time – Having one of each on every cycle breaks up combinational cycle 30 Penn ESE370 Fall2010 -- DeHon Register • Passhold on input latch samples value • Holdpass on output latch presents stored value to circuit Master and Slave latches 31 Penn ESE370 Fall2010 -- DeHon Class ended here 32 Penn ESE370 Fall2010 -- DeHon Register • How long from f1 rise to output? – At least part of clkoutput (tclk-q) 33 Penn ESE370 Fall2010 -- DeHon Clock Signal • Can we use a single signal for clock? 34 Penn ESE370 Fall2010 -- DeHon Clock Issues • Possible failure modes? – Flow through during transition? – Loading on clock phases – Delay in compute f1? 35 Penn ESE370 Fall2010 -- DeHon Appropriate Delay • Creates non-overlap • Too much could allow flow through 36 Penn ESE370 Fall2010 -- DeHon Clocking Discipline 37 Penn ESE370 Fall2010 -- DeHon Clocking Discipline • Follow discipline of combinational logic broken by registers • Compute – From state elements – Through combinational logic – To new values for state elements • As long as clock cycle long enough, – Will get correct behavior 38 Penn ESE370 Fall2010 -- DeHon This Week • Review tonight 7:30pm • Midterm Wednesday – No lecture – Midterm 7-9pm in this room • New homework out Thursday – Due Wed. next week • Class Friday 39 Penn ESE370 Fall2010 -- DeHon Ideas • Synchronize circuits – to external events – disciplined reuse of circuitry • Leads to clocked circuit discipline – Uses state holding element – Prevents • Combinational loops • Timing assumptions • (More) complex reasoning about all possible timings 40 Penn ESE370 Fall2010 -- DeHon