Machine Protection System

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Transcript Machine Protection System

LCLS Machine Protection System
Outline
Overview of interim MPS
Update on the interim MPS progress
Burst and single shot modes
Interim MPS schedule
Full MPS
Oct. 12, 2006
LCLS MPS
1
Stephen Norum
[email protected]
Overview of Interim MPS
Using existing infrastructure (1553 MPS)
Adding new signals and devices
Interim MPS will be used for gating beam
Single Shot Mode
Burst Mode
MPS algorithm is responsible for both LCLS and
CID beam
Pockels cell and MPS mechanical shutter limit
laser rate on cathode
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
1553 MPS
MPS device faults are input to Latching
Digital Input Modules (LDIMs)
Algorithms running in local processors (APs)
determine the max allowed rate based on
these faults
The supervisor (SP00) chooses the lowest
rate from the APs for the beam’s max
allowed rate
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Status
LDIM Assignments and MPS Database
LDIM channels have been assigned
VMS database has been built from these
assignments
Algorithm
Algorithm processor code is near completion
and is being reviewed
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Interim MPS Devices
Vacuum valves/status
Beam stoppers
Magnet power supplies
Profile monitors
Standalone toroid, toroid comparators
Flow switches and temperature monitors
Joule meter
Tone interrupt unit (TIU)
Protection Ion Chambers (PICs)
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Interesting Additions
MPS responsible for both CID and LCLS beam
BAS II stoppers are used to isolate LCLS
While BAS II stoppers are in
TIU is ignored as there are no devices between BX01 and TD11
Algorithm rate limits LCLS beam only
While BAS II stoppers are out
TIU works regularly—will zero rate all beams on any TIU fault
Algorithm rate limits both CID and LCLS beam
Algorithm switches modes automatically
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Interesting Additions
Burst and Single Shot Modes
Required for profile monitor acquisition
Burst mode—create a specified number of
pulses at a requested rate
Single shot—create a single pulse
Both modes are preceded and followed by no
beam
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Burst Mode
Implementation
EPICS IOC obtains three pieces of information
Number of pulses in burst
Burst Mode—a request to go enter burst mode
Burst Request—the request to allow beam
An event receiver (EVR) provides timing data to IOC
IOC uses the timing data to count pulses
When number of requested pulses have been created,
the IOC drops the burst request
Timing is handled by IOC, rate limiting logic is handled
by MPS algorithm
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Burst Mode Timing
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Burst Mode Logic
Burst Mode
Burst Request
Rate (Hz)
0
0
–
0
1
–
1
0
0
1
1
Burst Rate
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Single Shot Mode
Implementation similar to Burst Mode
“Counting” is done in hardware
A hardware flip-flop is set when single shot
mode is requested
When the single shot request is made, a pulse is
created
The trigger for this pulse clears the flip-flop,
ensuring only one pulse is created
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Interim MPS Schedule
Software
Oct. 12, 2006
LCLS MPS
SLC Database
- Device List
- LDIM Assignment
- Electrical Interconnect
MPS Algorithm
IOC
- Burst mode
- Single shot
- Digital IO Database
Creation
Date of Completion (2006)
Installation
Testing
Complete
Complete
Complete
Oct 23
Complete
Complete
Complete
Oct 24
Oct 13
Oct 13
Complete
Dec 07
N/A
N/A
N/A
Oct 23
Nov 15
Oct 11
Oct 18
Nov 23
Oct 13
Oct 20
Nov 22
Oct 11
Oct 20
Nov 22
N/A
N/A
12
Certification
Stephen Norum
[email protected]
Interim MPS Schedule
Date of Completion (2006)
Installation
Testing
Procurement
Hardware
Oct. 12, 2006
LCLS MPS
Linac PLIC
- PLIC Processor
PIC
- Power supply
- PICP
- PICs
Utilities
- Gas
IOC
- VME Crate
- EVR
- Transition Module
- Terminal Block
- IOC Cable
- IP Carrier
- IP 445
- IP 440
MPS Electronics
Shutter
- Shutter Controller
Pockels Cell
- Pockels Cell AND Gate
Faston
24V Power Supply
LDIM
Certification
Nov 01
Nov 03
Nov 06
N/A
Complete
Complete
Complete
Complete
Complete
Dec 06
Complete
Complete
Nov 01
Complete
Complete
N/A
Complete
Dec 06
Dec 07
N/A
Complete
Complete
Complete
Complete
Complete
Complete
Complete
Complete
Oct 11
Oct
Oct
Oct
Oct
Oct
Oct
Oct
Oct
Oct
Oct
Nov
Oct
Oct
Oct
Oct
Oct
Oct
Oct
Complete
Nov 15
Complete
N/A
Oct 25
Complete
Complete
Complete
Nov 03
Complete
Oct 13
Complete
Nov 01
Complete
Oct 11
Complete
N/A
N/A
Oct 11
N/A
13
18
18
18
18
18
18
18
18
13
16
22
16
16
16
16
16
16
11
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct 11
Stephen Norum
[email protected]
Full MPS Requirements
Strict timing requirement—respond to MPS
faults before next 120 Hz pulse (8.3 ms)
Multiple rate limits determined by fault
location
Automatic Recovery—if requested, raise
beam to before-fault rate after a fault is
corrected
Fault logic based on how quickly an
integrated loss threshold is exceeded
Oct. 12, 2006
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Stephen Norum
[email protected]
Simplified MPS Device Layout
(Note: Only PICs and PLICs shown. Many more devices are input to the MPS)
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Full LCLS MPS
New hardware developed by MRF
Modified VME-EVR-200 (VME-EVR-235)
Larger FPGA (XC2VP20)
2× logic cells, 1.5× IO, 2× PPC cores
Additional SFP transceiver and clock circuit
10/100 MAC/PHY
MMC Slot for Atmel Flash Card
128 MB SDRAM
Board has been ordered
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
VME-EVR-235
Micro-Research Finland Oy
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Full MPS Communication
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]
Full LCLS MPS
MPS hardware provides a high-speed
communication path back to EVG (2.5 Gbps)
The MPS’s mitigation path is independent of
the EVG and MPG, allowing the MPS to
quickly respond to faults
Design overview has been presented to
small group
Conceptual design review scheduled for
November 9th
Oct. 12, 2006
LCLS MPS
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Stephen Norum
[email protected]