Transcript ppt

Camera Electronics
- John Oliver Contributors to Camera Electronics conceptual design 2003-2006
• BNL – Veljko Radeka, Paul O’Connor
• Harvard – John Oliver, Christopher Stubbs
• Harvard Smithsonian CfA – John Geary
• Discussions & presentations at Camera and All-Hands meetings
Additional current contributors to Camera Electronics
• U. Penn (FEB)
• OSU (Fiber optics)
• ORNL/U. Tennessee (Sensor Control Chip)
• Brandeis (Timing & Control Module)
• LAL/LPNHE – Paris (ASPIC chip)
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Critical specs and decisions
Read noise
~ 5 e rms
Pixel read rate <
~500kPixels/sec
Modest segment
size ~ 1 MPixel
Read time ~
2 sec
High density
electronics  3,200
channels
FPA size 3,200
MPixels
Full well ~ 105
electrons
Short sensor to
preamp cables
Xtalk ~ 0.01%
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Critical specs and decisions
Read noise
~ 5 e rms
Place CCD driver ASICs
on FEBs near sensor
Read time ~
2 sec
Place Preamp/DSI ASICs
on FEBs near sensors
FPA size 3,200
MPixels
Preamps in cryostat as
close as possible to sensors
Full well ~ 105
electrons
Short sensor to
preamp cables
Xtalk ~ 0.01%
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Camera conceptual models – BEE in or out of cryostat
Cryostat
Sensors
Mains
Power
conversion
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FEE
FEB/BEB
connections
BEE
Data fibers
Timing &
Control
Ethernet setup & Command
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Decision time : BEE in or out?
• FEB to BEB connections : 24 differential analog, power ,bias, control
• 120 pins per FEB/BEB combination (redundant power pins)
• 6 FEB/BEB pairs per crate  720 pins per crate
• 25 crates  18,000 pins
BEE out of cryostat
1. 18,000 conductor
cryostat feedthroughs
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BEE in cryostat
1. ~ 30 conductor
feedthroughs per Raft
2. ~600 total
3. Shortest FEB/BEB
cables
4. 2x pcb area
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Decision time : BEE in or out?
• Concern about massive feedthrough count
• Judgment that additional pcb area in cryostat could be made
contamination free with suitable materials (polyimide) and
coatings (Parylene)
• Strict attention to contamination issue in Camera design &
materials certification
BEE in cryostat
1. ~ 30 conductor
feedthroughs per Raft
2. ~600 total
3. Shortest FEB/BEB
cables
4. 2x pcb area
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Additional features of baseline design
• Separation of functionality
o Front End
 Analog only
 - 100C thermal zone
 Back End
 ADCs, digital only, housekeeping, data formatting, data fiber output
 - 40C thermal zone
 ASIC based analog functions (Sensor Control Chip, ASPIC)
• Differential signaling only on interconnects : LVDS, differential analog
• Single timing source : Timing & Control module (outside cryostat)
• Fully synchronous readout : All rafts do the same thing at the same time
• Flexible and fully configurable “Readout State Machine” (FPGA based)
• Robust grounding : no ground loops within camera
• To outside world (CCS, DAQ) camera appears as
 Ethernet addresses for setup and high level command (eg “READ”)
 Mains power input
 Data fibers to DAQ
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Questions
1. Signal buffering on Sensor packages
a) Double source follower, single source follower, or external fet : Under
discussion with vendors
b) Critical spec is output impedance < ~ 1kW
c) Need low time constant on cable
2. Thermal control loop on sensor packages
a) Temp sensor on package
b) Heater resistors on package or thermal straps
c) Target +/- 1C absolute, +/- 0.1C stability
d) Heater dissipation ~ 0.25 to 0.5 W per sensor (biased at midpoint)
3. Electronics prototype effort
a) Low channel count discrete prototypes (Harvard/Penn)  Demonstrated
1.8 ADC count pedestal width
b) ASIC/ADC prototype (LAL/LPNHE)  Demonstrated electronic xtalk ~
0.007% , Noise performance “close” but problem understood in
simulations (1/f problem)
c) Full channel count BEE, partial channel count FEE ASIC based in progress
d) Raft tower, Raft Control Crate mechanical designs done, thermal models in
progress
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Questions
4. Contamination
a) Polyimide pcb technology
b) Parylene coating
c) SLAC materials certification facility
5. Synchronization
a) Each Raft Control Module (in RCC) is synched to a single common Timing
& Control Module with a single master clock (50 MHz)
b) Full synchronicity across focal plane to several nanoseconds skew, and subnanosecond jitter.
6. Xtalk
a) Measured electronic crosstalk ~ 0.007% from ASPIC through data output
interface
b) Will be dominated by sensor to preamp cable (high density design).
c) Modeling, designing, and testing of this cable interface is a critical item.
7. Power distribution, filtering, static protection
a) Power delivered separately to all rafts
b) Power sequencing envisioned for supplies in Utility Trunk
c) Filtering, bypassing, and sub-regulation done at all links in the chain.
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Questions
8. Electronic failures
a) Failure rate of silicon devices expected to be exceedingly low at reduced
temperatures.
b) Connector pins are expected to dominate  These have been chosen
exceedingly conservatively
c) Redundant pins when possible
d) Possible failure scenarios
i) Single channel (segment)
ii) Single “half sensor” (top or bottom row of 8)
iii) Single sensor
iv) Row of three sensors
v) Entire raft
vi) Diagnostics in place at many levels of the chain
e) Repair scenario
i) Modular construction
ii) Replace faulty crate (Raft Tower or Raft Control Crate)
iii) Service faulty crate/card/connector/cable in service facility and
recertify for future use.
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Questions
9. Power dissipation & heat removal
a) Radiated power through lens ~ ½ W per sensor
b) FEE electronic power ~ 1.5 W per sensor
c) BEE electronic power ~ 2 W peak, per sensor
d) Note: “Idle mode” available on both FEBs, and BEBs. Potential for
substantial power savings; active during READ only.
e) Turn-on times for Idle Mode for BEBs have been measured and are small
(~ mseconds)
f) All heat removal is through conduction
i) Chip scale packages where available
ii) Heavy thermal planes
iii) Heat transmitted to crate
iv) Taken out by cryoplate (Raft Tower) and coldplate (Raft Control
Crate)
v) Thermal models used during design and updated as necessary
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