Transcript slides

Muralidharan Venkatasubramanian
Vishwani D. Agrawal
Graduate Student
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University
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Purpose

Motivation
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Background
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Methodology
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Results
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Conclusion and Future work
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References
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Given a stuck-at fault, find a test.
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Specifically, find tests for hard to detect stuck-at faults.
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Derive a quantum computing algorithm to search
for test vectors.
 Increased interests in areas of probabilistic computing algorithms.
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Fault detection problem is NP complete [Ibarra and
Sahni, 1975; Fujiwara and Toida, 1982; Seroussi and
Bshouty, 1988].
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Various algorithms have been designed.
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D Algorithm [Roth, 1966]
PODEM [Goel, 1981]
FAN [Fujiwara and Shimono, 1983]
Many others…
Nature of NP complete problem implies Increasing
circuit size and complexity increases computation time.
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Generation of test vectors a classic VLSI problem.
 Tackled by numerous algorithms.
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Developed algorithms improve search over random
TPG.
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Test sets derived from functional description of circuits
can be too large [Akers, 1972 ; Reddy, 1973].
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Use of weighted random test generators
 Heuristics like input switching activity and weight assignment
[Schnurmann et al., 1972].
 Skewing input probability to attain maximum output entropy
[Agrawal, 1981].
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Using spectral properties of successful vectors to
generate new vectors [Yogi and Agrawal, 2006].
 Implementing Hadamard matrices for Walsh functions.
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Search limits when searching for unique test vectors
of hard to detect faults.
 Problem devolves back to NP hard problem.
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Proposed solution uses probabilistic correlation
among primary inputs.
 Skew the search in the test vector space.
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Correlation present between input test vectors [Akers,
1972].
Because we are testing hard-to-detect faults, we
generally have many trial vectors that do not work.
Conjecture is to find test vectors with properties not
similar to the preciously found vectors.
 Ignore vectors with properties similar to known unsuccessful
test vectors.
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Use opposite correlation to extract the likely test
vectors.
 Skew the search in the test vector space for the correct test
vector.
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Quantify correlations in an n x n probability matrix.
 n is the no. of primary inputs.
 Diagonal represents independent probability of ‘0’ or ‘1’ at
primary input.
 An off-diagonal entry represents conditional probability of
‘0’ or ‘1’ at other inputs given a state at the chosen primary
input.
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Correlation matrix contains information from
unsuccessful test vectors.
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c17 benchmark circuit
 5 primary inputs
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Initially, apply random
vectors to the CUT so
as to build an initial
table of unsuccessful
vectors.
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Initial Test vectors derived from random TPG
01100
Probability Correlation Matrix
10001
A 0.66 0
0.50
1
1
10110
Input signal probability
Input signal probability
conditional to
corresponding input
being ‘1’
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B
0
C
0.50
1
0.66
D
0.50
0
0.50 0.33
E
0.50
0
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0.33 0.50
0
0
0
1
0
0
0
0.33
12
A
B
C
D
E
0.66
0
0.5
0.5
0.5
0
1
x
x
x
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
1
A
0.40
B
0
0.33 0.33 0.50
0.60 0.66 0.66 0.50
C
0.50 0.66 0.60 0.66 0.50
D
0.50 0.66 0.66 0.60 0.50
E
0.50 0.33 0.33 0.33 0.40
Add the two derived test vectors to the
original set and recalculate the matrix
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Recalculated Probability
Correlation Matrix
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A
0
B
C
D
E
0.60 0.66 0.66 0.33
1
0
0
0
x
1
0
0
0
0
1
0
0
0
1
Final test vector set:
01100
10001
10110
01010
01111
10000
Final test vector
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Mean = 566
Average no. of iterations needed to find a single
stuck-at fault using a random test generator
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Mean = 26
Average no. of iterations needed to find a single stuck-at fault
using a weighted random test generator [Agrawal, 1981]
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Mean = 9
Average no. of iterations needed to find a single stuckat fault using the proposed correlation algorithm
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C17 benchmark circuit
 Had no hard to detect stuck-at faults
 Proposed correlation algorithm took ~24-30 iterations to detect 12
faults (3 vectors) with worst case of 44 iterations.
 FastScan needed 64 iterations with worst case of 128 iterations.

C492 benchmark circuit (27 primary inputs)
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Fault no.
Correlation
Algorithm
iterations
1
3180
2
1864
3
3179
4
1865
FastScan
iterations
Average
iterations
needed
Could not
compute
227/2 = 226
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Optimizing the algorithm for more efficiency.
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Running simulations on all ISCAS benchmark circuits.
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Comparing efficiency with other contemporary and
deterministic algorithms to prove superiority.
 Weighted random generators
 Spectral test generators
 Anti-random test generators [Malaiya, 1995]
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Foray into quantum algorithms (future vision).
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Demonstrated proof of concept of new probabilistic
correlation algorithm.
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Shown resilience compared to previously published
output entropy based algorithm.
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Initial results show the superiority of algorithm over
FastScan for hard to detect stuck-at faults.
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Vision of future direction research and identifying
steps towards a quantum algorithm.
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[1] O. H. Ibarra and S. Sahni, “Polynomially complete fault detection
problems,” IEEE Trans. Computers, vol. 24, no. 3, pp. 242–249, 1975.
[2] H. Fujiwara and S. Toida, “The complexity of fault detection problems for
combinational logic circuits,”IEEE Transactions on Computers, vol. 100, no. 6,
pp. 555–560, 1982.
[3] G. Seroussi and N. H. Bshouty, “Vector sets for exhaustive testing of logic
circuits,” IEEE Transactions on Information Theory, vol. 34, no. 3, pp. 513–522,
1988.
[4] J. P. Roth, “Diagnosis of automata failures: A calculus and a method,” IBM
Journal of Research and Development, vol. 10, no. 4, pp. 278–291, 1966.
[5] P. Goel, “An implicit enumeration algorithm to generate tests for
combinational logic circuits,” IEEE Transactions on Computers, vol. 100, no. 3,
pp. 215–222, 1981.
[6] H. Fujiwara and T. Shimono, “On the acceleration of test generation
algorithms,” IEEE Transactions on Computers, vol. 100, no. 12, pp. 1137–1144,
1983.
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[7] S. B. Akers, “Universal test sets for logic networks,” in IEEE Conference
Record of 13th IEEE Annual Symposium on Switching and Automata Theory,
1972, pp. 177–184.
[8] S. M. Reddy, “Complete test sets for logic functions,” IEEE Transactions
on Computers, vol. 100, no. 11, pp. 1016–1020, 1973.
[9] H. D. Schnurmann, E. Lindbloom, and R. G. Carpenter, “The weighted
random test-pattern generator,” IEEE Transactions on Computers, vol. 100,
no. 7, pp. 695–700, 1975.
[10] V. D. Agrawal, “An information theoretic approach to digital fault
testing,” IEEE Transactions on Computers, vol. 30, no. 8, pp. 582–587, 1981.
[11] N. Yogi and V. D. Agrawal, “Spectral RTL test generation for gate-level
stuck-at faults,” in Proc. 15th Asian Test Symposium, IEEE, 2006, pp. 83–88.
[12] Y. K. Malaiya, “Antirandom testing: Getting the most out of black-box
testing,” in Proc. Sixth IEEE International Symposium on Software Reliability
Engineering, 1995, pp. 86–95.
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