Transcript Sheth
ELEC 7250 Term Project Presentation Khushboo Sheth Department of Electrical and Computer Engineering Auburn University, Auburn, AL Problem 1 • Problem statement: Develop a compiler for the hierarchical format with 2 options for the user : Default option and Hierarchical option • Algorithm used: • User is asked for the circuit and the option • Hierarchical Option: – Hierarchical file read line by line and HierSim file having the Hierarchical simulation table is given to the user. • Default Option: – The different Hierarchical blocks are stored as an element in the block array and as the hierarchical netlist is read the blocks are flattened and stored in the Object file having the flat netlist. – This Object file is then read to create the Flat simulation table in FlatSim file. Problem 2 • Problem Statement: Develop a logic Simulator for combinational circuits consisting of zero-delay Boolean gates with hierarchical bench format netlist input and fully specified input vectors and expected responses. • Algorithm used: • Firstly, given circuit is fed to the levelizer where the unlevelized circuit is levelized. • Levelized circuit simulated by reading the given netlist line by line and performing the specified operations. Problem 3 • Problem Statement: Introduce a design error in the netlist and have the simulator list the failing vectors and POs where errors are observed. • Algorithm used: • The circuit netlist and the fully specified input vectors and the expected responses is taken from the user. • Simulator reads the input vectors from the given input file and operates with those vectors, the calculated responses are then compared with the expected responses. • If the circuit is faulty the list of failing vectors and POs where the errors are observed is then given to the user. Problem 4 • Problem Statement: Attempt to diagnose the design error. • Algorithm used: • Once again, the circuit netlist and fully specified input vectors and the expected responses is taken from the user. • The circuit is levelized by the levelizer • The circuit is then diagnosed for faults • The simulator compares the calculated responses of the given vectors with the expected responses. • The comparison with the true circuit and the back trace from the primary failing output is used for the diagnosis. Results of the Simulation of 4-bit adder circuit 700 time in msecs 600 500 400 300 200 100 0 56 ips 100 ips 156 ips no. of input vectors 200 ips 256 ips Results of the Simulation of ISCAS`85 circuits 2500 1500 1000 500 iscas`85 circuits c7 55 2 c6 28 8 c5 31 5 c3 54 0 c2 67 0 c1 90 8 c1 35 5 c8 80 c4 99 c4 32 0 c1 7 Time in msecs 2000 Conclusion • Execution time increases with the number of gates and number of input vectors • Diagnosis Algorithm can be improved for better results. Thank You !!!