Transcript slides
Reducing Switching Capacitance Using Buffers Brad Hill Dec. 6, 2005 ELEC6970-001 Class Presentation 1 Objective Reduce the Power of a Multiplier Circuit Do this with out Increasing the Delay of the Critical Path Dec. 6, 2005 ELEC6970-001 Class Presentation 2 Problem of Fanout Fanout Increases the Capacitive Load on the Driving Transistor RC time constant increases due to increased load capacitance Delay of the circuit increases Dec. 6, 2005 ELEC6970-001 Class Presentation 3 Reasoning Behind Buffers Single Fanout There is a steady increase in transistor size between stages Extra Large Drive Transistors The transistor driving the buffer now sees a single fanout instead of a large fanout Reduce Charging Resistance Increase Drive Capacity Lowers the RC time constant and speeds up the switching to reduce delay This does not directly reduce power but can be used to our advantage Dec. 6, 2005 ELEC6970-001 Class Presentation 4 2x Buffer Dec. 6, 2005 ELEC6970-001 Class Presentation 5 Multiplier Simulated cells and circuits with multiple cells compared results Found the best configuration of the buffers in the circuits to reduce the delay Dec. 6, 2005 ELEC6970-001 Class Presentation 6 Critical Path Dec. 6, 2005 ELEC6970-001 Class Presentation 7 Cell with Buffers • The fanout of both Sum_in and Carry_in in the Cell is 6 • These two signals benefit the most from buffers Dec. 6, 2005 ELEC6970-001 Class Presentation 8 Delay of a Cell without Buffers (1.8V) Dec. 6, 2005 ELEC6970-001 Class Presentation 9 Cell with Buffers (1.8V) Dec. 6, 2005 ELEC6970-001 Class Presentation 10 Cell Delay (1.75V) Dec. 6, 2005 ELEC6970-001 Class Presentation 11 Cell With Buffer Delay (1.75V) Dec. 6, 2005 ELEC6970-001 Class Presentation 12 Comparison Dynamic(W) Static(W) Delay(S) Supply Voltage Single Cell 33.86u 171.14p 14.942p 1.8V Cell with buffers 35.08u 243.98p -129.56p 1.8V No Buffers 31.44u 162.10p 16.129p 1.75V Buffers 32.34u 230.87p -120.778p 1.75V Difference -1.52u 59.73p -135.72 -0.05V Dec. 6, 2005 ELEC6970-001 Class Presentation 13 Two Cells with Buffers • The two cells represent two cells in the middle of the multiplier • A, B, B1, Sum_in, Carry_in, and Sum_in1 are driven for the simulation Dec. 6, 2005 ELEC6970-001 Class Presentation 14 Cells 1.8V Dec. 6, 2005 ELEC6970-001 Class Presentation 15 Cells no Buffers 1.75V Dec. 6, 2005 ELEC6970-001 Class Presentation 16 Cells with Buffers 1.75V Dec. 6, 2005 ELEC6970-001 Class Presentation 17 Two Cell Simulation Comparison Dec. 6, 2005 Dynamic( Static(W) W) Delay(S) Supply Voltage No Buffers 467.126u 342.282p 12.081p 1.8V Buffers 488.136u 487.96p -7.85p 1.8V No Buffers 418.677u 324.2060 p 13.510p 1.75V Buffers 438.90u 461.75p 5.095p 1.75V Differenc e -28.226u 119.552p -6.986p -0.05V ELEC6970-001 Class Presentation 18 Area of Cell Dec. 6, 2005 Gate Area AO32 288 XOR 310 XNOR 282 NAND 88 Total 968 ELEC6970-001 Class Presentation 19 Increase in Area Area of a 2x Buffer Area of Buffered Cell 84 1136 Percent Increase 17.36% Dec. 6, 2005 ELEC6970-001 Class Presentation 20 Conclusions Strategically placed buffers can greatly decrease the delay of a circuit This reduction in delay can be used to offset the increase in delay due to some power reduction schemes Dec. 6, 2005 ELEC6970-001 Class Presentation 21