Transcript Built-In Self-Test of Global Routing Resources . . . Yao

BUILT-IN SELF-TEST OF GLOBAL
ROUTING RESOURCES IN VIRTEX-4
FPGAS
Jia Yao, Bobby Dixon, Charles Stroud and
Victor Nelson
Dept. of Electrical & Computer Engineering
Auburn University
Outline of Presentation
 Motivation and background
 Virtex-4 global routing resource
 Routing BIST Implementation
for Virtex-4 FPGAs
 Implementation results
 Application to Virtex-5
 Summary
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North Atlantic Test Workshop
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Fault Simulation Results
w/ ORA
w/o ORA
100
Stuck-at Fault
90
Stuck-at value
Feedback wires
can be considered
under test
Fault Coverage (%)
80
70
60
50
40
30
20
10
0
Single
Counter
Dual Counter
Dual Parity
Dominant BFs
100
CrossCoupled
Parity
All 150-Rule
CAR
Dominant-AND/OR BFs
18
90
Max Length
CAR
19
8
24
Fault Coverage (%)
80
70
60
Bridging Fault
Best approaches
6
8-bit maximum length
sequence CAR
 cross-coupled parity
8
50
40
30
20
10
0
Single
Counter
Dual Counter
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Dual Parity
CrossCoupled
Parity
Max Length
CAR
All 150-Rule
CAR
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Cross-Coupled Parity Approach
ORA (Oo)
odd parity
ORA
even parity
Slice 3
ORA (Oe)
even parity
ORA
odd parity
2
1
TPG (To)
count-down
odd parity
Slice 1
Podd
Cu1
Cu0
G LUT
Peven
Cd1
Cd0
G LUT
Pass
/Fail
Test Pattern Sequence
Cu1Cu0 Po Cd1Cd0 Pe
00
1
11
0
Pass
01
0
10
1
/Fail
10
0
01
1
11
1
00
0
Podd
Cd1
Slice 2
G LUT
Cu1
Cd0
2
1
TPG (Te)
count-up
even parity
Peven
G LUT
F LUT
Cu0
Slice 0
F LUT
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Virtex-4 Global Routing Resources
CLB
 Switch Box
 Slices (LUTs & FFs)
N/S 2 BEG 0-9
 PIPs
Switch Box
slices
Double/Hex lines
 N/S/E/W
N/S 2 MID 0-9
 10 wires
N/S 2 END 0-9
 BEG, MID, END
Long lines
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Long Lines
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BIST for Double lines (North and South)
BEG 0-9
Te
MID 0-9
Oo
Oe
To
END 0-9
Oo
Oe
BEG 0-9
To
MID 0-9
END 0-9
BEG 0-9
MID 0-9
END 0-9
J. Yao 5/15/08
Oo
Oe
Te
Oe
Oo
Test Pattern Sequence
Cu1Cu0 Po Cd1Cd0 Pe
00
1
11
0
01
0
10
1
10
0
01
1
11
1
00
0
 Pass by 1 CLB into MID
pass by 2 CLBs into END
6 wires under test (2 configs)
Te
12 lines under test in parallel
Oo
Oe
 Alternate TPGs, ORAs position
To
in adjacent CLBs.
Oo
Oe
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Loopbacks
Loopback
Connections
 At the edges of array
 via wires in the opposite
South
END-to-BEG
Connections
direction till the opposite
edge
 Example:
north double lines
loopback at the top edge
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BIST for Double lines (East and West)
 Involve Non-CLB Columns
 END and BEG terminals in east and west directions
are connected
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Non-CLB Column Double Lines
BIST for Non-CLB
Column Double Lines
TPGs and ORAs locate in
adjacent CLB columns
Use east/west double
lines to connect adjacent
CLB columns
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North Atlantic Test Workshop
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BIST For Hex Lines
 Hex lines architecture
 pass by 3 CLBs into MID, by 6 CLBs into END
 more limitation of connections from hex lines to LUTs
 MID and END terminals share the same PIPs
 BIST for hex lines
similar to double lines
 more configurations needed
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Long Lines Architecture
i+25
i+24
 pass by 24 CLBs
i+19  5 wire segments
i+18
4 wires under test
i+13 Bi-directional
i+12
i+7
i+6
 two end points: source or input
 other three stops: input only
 Orthogonal direction is
tested simultaneously
i+1
i
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BIST for Long lines
Peven
Oe
CLB i+24
Cu2
CLB i+5
Tcu
Oe
Oe
CLB i+4
CLB i+18
Tcd
Oe
Cu1
Oe
CLB i+12
Cuo
Oe
CLB i+3
Tcu
Oe
CLB i+2
CLB i+6
Tcd
Oe
Peven
CLB i+1
Oe
Tcu
Oe
CLB i
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Tcd
Oe
Pass
/Fail
G LUT
Peven
Cd0-3
F LUT
ORA
even parity
(Oe)
TPG count-up
even parity (Tcu)
TPG count-down
even parity (Tcd)
Cu2 Cu1 Cu0
Cd2 Cd1 Cd0
Peven
Peven
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
1 0 1
0
0 1 0
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
CLB i
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Global Routing BIST Configurations
Routing
Resource
Direction
N
S
E
W
CLB double lines
2
2
2
2
Non-CLB column double lines
2
2
CLB hex lines
4
4
Non-CLB column hex lines
2
2
CLB long lines
*
*
Non-CLB column long lines
1
1
Total BIST Configurations
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Total
Configs
8
4
2
2
12
4
1
1
2
2
32
13
Actual Implementation Results
RAM
RAM
DSP
I/O Cell
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MIDDLE
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Application to Virtex-5
Global Routing Resource changed
 double lines, pent lines and long lines
 N/S/E/W
 BEG, MID, END
 half as the same, half as “L-shaped” which go in
orthogonal direction as well
 3 wires for each pattern in each direction
instead of 10
 long lines pass by 18 CLBs, four wires
 Our approach is adapted to Virtex-5
 test for “L-shaped” double/pent lines
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Summary
Cross-coupled Parity is the best choice
better fault coverage
the most practical for actual implementation
best choice for Virtex-5
 BIST of Virtex-4 routing resources
Program to generate BIST configurations
automatically
modified for V-5
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