Transcript Presentation 4/24/07

CPU Design Project
Synthesis Report
ELEC 7770-001 - Dr. Agrawal
Lee W. Lerner
April 24, 2007
Outline


Synthesis Goals
Synthesis Design Flow
• Mentor Graphics IC Flow Design Tools
• Various other software tools used for design
debugging and verification

Synthesis Results
• Area and Delay reports
• Netlist verification

Conclusions
• Suggestions for improvement
Synthesis Goals


Take a verified design modeled in
hardware description language (VHDL in
our design project)
Generate a gate- level netlist for the
circuit that optimizes either:
• 1. Area
• 2. Delay
• 3. Both (to a lesser extent)


Verify functionality of netlists generated
Decide on synthesized netlist to proceed
with in project design flow
Synthesis Design Flow

Mentor Graphics IC Design Flow tools
used:
• Leonardo Spectrum 8

Synthesize gate-level netlists optimized for
area and delay from provided VHDL CPU
design
• Flextest

Verify that synthesized gate-level netlists
compile
Synthesis Design Flow

Leonardo Spectrum 8
V. P. Nelson, Tutorial Documents for Mentor Graphics Tools,
http://www.eng.auburn.edu/department/ee/mgc/mentor.html
Synthesis Design Flow

Netlists generated and corresponding
reports:
• 1. Area Optimization (CPU_areaOpt.edf)
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Area report: areaOpt_areaReport
Delay report: areaOpt_delayReport
• 1. Delay Optimization (CPU_delayOpt.edf)
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Area report: delayOpt_areaReport
Delay report: delayOpt_delayReport
Synthesis Results

areaOpt_areaReport
Synthesis Results
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areaOpt_delayReport
Synthesis Results
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delayOpt_areaReport
Synthesis Results

delayOpt_delayReport
Synthesis Results

Netlist comparison
Area Optimization
Delay Optimization
Number of ports
111
Number of nets
8249
Number of instances
7601
Number of references to this view
0
Number of gates
16264
Number of accumulated instances
7601
data arrival time
18.06 ns
Number of ports
111
Number of nets
8343
Number of instances
7696
Number of references to this view
0
Number of gates
16280
Number of accumulated instances
7696
data arrival time
18.22 ns
Synthesis Results

Synthesis Verication: FlexTest


Netlists
compile
correctly
Need for
DFT (scan
design)
Conclusions
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
Used Leonardo Spectrum 8 to
generate gate-level netlists
optimized for area and delay
independently
Netlists compile correctly
Due to area and delay similarity
between generated netlists it was
decided that we could proceed with
either netlist in the design project
Conclusions

Suggestions for improvement
• Improved communication between team
members (i.e. weekly status
reports/presentations)




Every team member has input at each stage
in the design
Identify coding and design errors earlier
Identify need for and implement DFT before
synthesis
Improved CPU design in a shorter time