Transcript slides
High-Level Design and ESL:
Who Cares?
Organizer: Carl Pixley, Synopsys
Moderator: Alan J. Hu, University of British Columbia
VLSI Design in the 1960s
Designer figures out desired structures.
Designer creates masks by hand (literally)
with Rubylith and X-acto knife
CAD industry: There must be a better way!
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VLSI Design in the 1970s
Designer dreams up physical layout.
Designer draws layout on CAD workstation.
CAD tool separates layers and plots masks.
3
VLSI Design circa 1980
Designer dreams up gates.
Designer draws gate-level schematic on CAD
workstation.
CAD tool maps gates to standard cells, does
channel routing.
CAD tool separates layers and plots masks.
4
VLSI Design in the late 80s
Designer writes synthesizable RTL.
CAD tool does logic synthesis to gate-level
schematic.
CAD tool maps gates to standard cells.
CAD tool separates layers and plots masks.
always @posedge(clk) begin
...
end
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VLSI Design in the 1990s
Designer writes synthesizable RTL.
CAD tool does logic synthesis to gate-level
schematic.
CAD tool maps gates to standard cells.
CAD tool separates layers and plots masks.
Research on high-level synthesis, behavioral
synthesis…
6
VLSI Design circa 2000
Designer writes synthesizable RTL.
CAD tool does logic synthesis to gate-level
schematic.
CAD tool maps gates to standard cells.
CAD tool separates layers and plots masks.
Research on high-level synthesis, behavioral
synthesis, C for hardware design,…
7
VLSI Design since 2000
Designer writes synthesizable RTL.
CAD tool does logic synthesis to gate-level
schematic.
CAD tool maps gates to standard cells.
CAD tool separates layers and plots masks.
Research on high-level synthesis, behavioral
synthesis, C for hardware design, ESL, TLM,
…
8
VLSI Design in 2010?
Designer writes synthesizable RTL.
CAD tool does logic synthesis to gate-level
schematic.
CAD tool maps gates to standard cells.
CAD tool separates layers and plots masks.
Research on high-level synthesis, behavioral
synthesis, C for hardware design, ESL, TLM,
???, ???, ???, …
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EDA Market Sizes
How big is the verification market?
$800 Million
How big is the ESL synthesis market?
$16 Million
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High-Level Design and ESL:
Who Cares?!?
Panelists
Masahiro Fujita
Professor, University of Tokyo
Anmol Mathur
Founder and CTO, Calypto Design Systems
Rajesh Gupta
Professor and QUALCOMM Chair, UCSD
Kris Konigsfeld
Senior Principal Engineer, Intel
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Masahiro Fujita
Professor, VLSI Design and Education Center,
University of Tokyo
Previously, Director of VLSI CAD,
Fujitsu Laboratories of America
Research on Design, Verification, and Test
7 Books, 100+ Papers
Research Awards from Japanese Scientific
Societies
PhD 1985, University of Tokyo
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Anmol Mathur
CTO and Founder, Calypto Design Systems
Previously, Architect of Datapath Synthesis and
Optimization, Ambit Design Systems and Cadence
Before that, developed and deployed RTL-to-gate
equivalence checker at MIPS/SGI
MS and PhD from UIUC
BTech, IIT, Gold Medal
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Rajesh Gupta
Professor, QUALCOMM Endowed Chair, UCSD
Previously, Professor at UC Irvine and UIUC
Circuit Designer at Intel
Research on CAD at Different Abstraction Levels
Chancellor’s Fellow, Chancellor’s Award at UC
Irvine, NSF CAREER, IEEE Fellow, etc.
Founding Chair MEMOCODE
Founding Co-Chair CODES+ISSS
Editor-in-Chief, IEEE Design and Test
PhD Stanford, MS UC Berkeley, BTech IIT Kanpur
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Kris Konigsfeld
Senior Principal Engineer, Intel
Intel Achievement Award
Nehalem Architecture Operations Manager
CAD Tool Suite for Pentium 4 and Itanium
Memory Order Buffer Unit, Pentium Pro
Silicon Design Engineer, iWarp
BS, MS UIUC
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Panelists
Masahiro Fujita
Professor, University of Tokyo
Anmol Mathur
Founder and CTO, Calypto Design Systems
Rajesh Gupta
Professor and QUALCOMM Chair, UCSD
Kris Konigsfeld
Senior Principal Engineer, Intel
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Real History of VLSI
Design
High-Level
High-Level vs. RTL
Equivalence Checking
RTL
Formal Equivalence Checking
Gates
LVS
Layout
Fab
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