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A Low-Voltage Low-Power Sigma-Delta
Modulator for Broadband Analog-to-Digital
Conversion
IEEE Journal Of Solid-state Circuits, Vol. 40, No. 9, September 2005
Kiyoung Nam, Student Member, IEEE, Sang-min Lee, Student Member, IEEE, David K. Su, Senior Member,
Ieee,and Bruce A. Wooley, Fellow, IEEE
Wei-Chih
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Outline
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Abstract
Introduction
Architecture
Power minimization
Implementation
Measurements
Conclusion
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Abstract
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A cascade(2-2) of sigma-delta modulator with employ a feedforward
architecture and date weighted averaging (shifter).
Dynamic range of 96 dB for a 1.25-MHz signal bandwidth.
The implement in 0.25μm CMOS technology
 Analog power dissipation is 44mW.
 Digital power dissipation is 43mW.
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Introduction
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Considerations of cost and performance.
 Cost:
 Reduction in supply voltage.
 Advanced CMOS technologies problematic.
 Systematic means of power minimizing .
 Noise-and-settling constrained power minimization (NSCPM).
 Performance:
 Limited of supply voltage available.
 Circuits limited by thermal noise, noise floor.
 Leads to an increase in power dissipation.
 To achieve the targeted performance objectives.
 Architectural to maximizing the input signal range in ΣΔ
modulator.
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Architecture (cont.)
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Conventional first-order ΣΔ modulator.
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First-order reduced integrator swing range (RISR) ΣΔ modulator.
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Architecture (cont.)
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A large signal at the integrator output causes three problems.
(Conventional)
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Distortion
 Results from the clipping of integrator output.
 To maintain a given dynamic range. (Power↑)
Harmonics
 Associated variation of op amp dc gain.
 Gain enhancement. (Power↑)
OP architectural. (Same gain and bandwidth)
 Single-stage.
 Two-stage.
(Power↑)
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Architecture (cont.)
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RISR ΣΔ modulator architecture.
 Advantages
 The signal ranges required for
and can be greatly reduced
by
.
 Smaller
avoids op amp slewing. (Power↓)
 Smaller
is favorable at low supply voltages.
 Single-stage OP. (Power↓)
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is now decoupled from the input .
 A large full-scale input range can be used. (Power↓)
 The op amp dc gain and settling time constant requirements are
greatly relaxed.
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Architecture (cont.)
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RISR ΣΔ modulator architecture.
 Quantization error
 Large swings in
are not problematic because this signal
immediately precedes the quantizer.
Second-order reduced integrator swing range (RISR) ΣΔ modulator.
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Architecture (cont.)
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Maximum magnitudes of integrator inputs and outputs versus input level
for different second-order ΣΔ modulator topologies.
1st input
1st output
2nd input
2nd output
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Architecture (cont.)
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Maximum magnitudes of integrator inputs and outputs versus OSR for
different second-order ΣΔ modulator topologies.
1st input
1st output
2nd input
2nd output
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Architecture (cont.)
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RISR ΣΔ modulator architecture.
 Disadvantages
 The timing overhead is greater.
 Because the delay from the feedback.
 Increased power dissipation in the comparators. (Quantizer)
 Fast amplification and regeneration.
 Small input-referred offset.
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This power penalty is small in comparison with the power saved in the
op amps used to implement the integrators.
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Architecture
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The RISR architecture can be expanded.
 Order = L .
 Bits = N. (N ≥ L )
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= minimize.
To avoid the op amp slewing.
= Maximize.
To minimize the power dissipation.
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Power minimization (cont.)
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The procedure is described by the flow graph.
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MIDAS
 Op amp dc gains.
 Settling time constants.
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Power minimization (cont.)
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Integrator Settling.
The input-referred thermal noise power of a switched-capacitor
integrator.
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Power minimization (cont.)
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NSCPM algorithm.
Minimization of the sum of the two integrator transconductance (17) is
the objective or cost function of the NSCPM procedure.
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Power minimization (cont.)
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NSCPM results
 _
30
0.598
12.8pF
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12.8pF
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Power minimization (cont.)
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First integrator noise distribution between the switch noise and the op
amp noise versus
.
Circuit parameters:
=54mS ,
=12.8pF,
=30Ω.
=5.8mS ,
=2.8pF ,
=71Ω.
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12.8pF
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Power minimization
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Final architecture.
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Implementation (cont.)
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First stage.
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Op amp for the first integrator.
The final op amp at least 57 db of gain across all process corners.
Four integrators in the two-stage cascade are scaled in succession by 1,
1/4, 1/16, and 1/32.
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Implementation
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Comparator for the first and second quantizers.
Signal:
:
store the preamp offset,
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cancel offset.
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Measurements (cont.)
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DR of 96 dB was achieved with a
peak SNDR of 89 dB at 366-kHz
BW.
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SFDR of 97 dB with 109-kHz BW
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Measurements
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Summary of measured performance
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Conclusion
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The use of a (RISR) modulator architecture
 Minimizes the signal ranges required at the inputs and outputs of the
forward-path integrators.
 Single-stage op amp implementation of these integrators, even at low
voltage.
The power minimization procedure (NSCPM) has the added advantage of
providing quantitative information about the trade-off between power,
linearity, and area.
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