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A Prototype FPGA Tile for SubthresholdOptimized CMOS Peter Grossmann, Miriam Leeser • Low power systems benefit from FPGAs – – – Improved energy efficiency/performance vs. microcontroller Improved design via reconfigurability Lower cost vs. ASIC • State of the art low power FPGAs: 10s to 100s of mW • Ultra-low power applications require 10s to 100s of µW – – – • Wireless sensor networks RFID Digital hearing aids Ultra-low power budgets motivate extreme voltage scaling – Subthreshold supply voltages yield peak energy efficiency This work is funded by the Lincoln Scholars Program, MIT Lincoln Laboratory. The Lincoln Laboratory portion of this work was sponsored by the United States Government under Air Force contract number FA8721-05-C0002. The opinions, interpretations, conclusions and recommendations are those of the authors and are not necessarily endorsed by the United States Government. HPEC_2010-1 PJG 9/15/2010 MIT Lincoln Laboratory APPROVED FOR PUBLIC RELEASE – DISTRIBUTION IS UNLIMITED Subthreshold vs. Superthreshold Circuits H yp o th e tic a l M O S I-V C u rv e Key Tradeoffs in Subthreshold Operation: 0 .0 0 1 0 .0 0 0 1 · High energy efficiency D ra in C u rre n t (A ) 1 E -0 5 1 E -0 6 · Large circuit delays 1 E -0 7 VTH 1 E -0 8 1 E -0 9 · High sensitivity to process variation 1 E -1 0 1 E -1 1 1 E -1 2 0 0 .2 0 .4 0 .6 0 .8 1 1 .2 1 .4 1 .6 G a te -S o u rc e V o lta g e (V ) ID I0 W L V GS V TH e nV T V DS V 1 e T Subthreshold HPEC_2010-2 PJG 9/15/2010 ID I0 W L V GS V TH 2 · Low sensitivity to transistor size · High sensitivity to supply voltage Superthreshold MIT Lincoln Laboratory APPROVED FOR PUBLIC RELEASE – DISTRIBUTION IS UNLIMITED Prototype Tile Architecture • 2-input CLB Tile Boundary • 4 routing channels 24 SRAM, Programming Circuitry ASEL[1] ASEL[0] • YSEL[0] A 32 programming bits YSEL[1] CLB ASEL[0] Y YSEL[2] • BSEL[0] Flexible I/O BSEL[1] YSEL[3] B BSEL[0] HPEC_2010-3 PJG 9/15/2010 MIT Lincoln Laboratory APPROVED FOR PUBLIC RELEASE – DISTRIBUTION IS UNLIMITED Prototype Tile Demonstration A B 00 01 10 11 0 1 1 0 00 01 10 11 0 1 1 0 D Q • Functional verification of all tile components through implementation of serial adder • Tile average power ≈ tens of nanowatts • Enables useful circuits on sub-mW power budgets • Implementation of 6x6 tile array on test chip currently in fabrication at Lincoln Laboratory SUM CIN 00 01 10 11 00 01 10 11 0 0 0 1 00 01 10 11 0 0 0 1 Serial Adder HPEC_2010-4 PJG 9/15/2010 0 1 1 1 D Q COUT MIT Lincoln Laboratory APPROVED FOR PUBLIC RELEASE – DISTRIBUTION IS UNLIMITED