Transcript EMU Sept. 18, 2006

VCC Hardware Production Status
Production VCC Locations and Dispositions
Location
D
i
s
p
o
s
i
t
i
o
n
CERN
OSU
RICE
Florida
Total
Total
50
23
1
1
75
In Per. Crate
?
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---
---
?
Test Setups
?
2
1
1
4+
Waiting for BGA
Replacement
---
3
---
---
3
Testing/Repair/Burn-in
---
15
---
---
15
Ready to Ship
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3
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3
All components have arrived and all boards are stuffed.
Most of the boards currently being tested should be ready to
ship by the end of this week.
J. Gu
EMU Meeting, CERN
Sept. 18, 2006
1
Reported VCC Related Issues
Ref. #
1
Issue
Cause
Resolution
DMB EPROM load
Sperious Bus Request when
executing ‘DELAY’ command
Vcore boosted (improved failure rate)
ISE 8.202i (gone with new compile)
2
TMB-CFEB timing
test
Multiple DLink driver conflicts.
Changes to ethreset
3
9TMBs-to-MPC test
VME SYSCLK disabled
(problem for MPC during Hard Resets)
Changed power up configuration to
enable SYSCLK
Valid data flag not set
Vcore boosted (problem gone)
4
BERR/missing data
•Vcore (1.5V +/- 5%) was out of tolerance due to Vdrop across inductor.
•Boosting Vcore solved issue 4 but only decreased the frequency of issue 1.
•Recompiling (with no logic changes) using ISE 8.202i appears to have ‘fixed’
issue 1 but other compile issues have arisen (still investigating).
•Issue 2 has not reoccurred and does not appear to be a VCC issue.
•Issue 3 was simply a user configuration setup issue.
J. Gu
EMU Meeting, CERN
Sept. 18, 2006
2
VCC Items to be done
Replace resistor for 1.5V regulator.
Add 10 uF Tant. bypass caps for oscillators (these
were omitted during original board assembly).
Continue firmware development to provide packet
acknowledgements and ethernet firmware
downloading.
J. Gu
EMU Meeting, CERN
Sept. 18, 2006
3