Transcript A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture

A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW
Power Realized by a High Bandwidth Scalable
Time-Interleaved Architecture
Sandeep Gupta, Michael Choi, Michael Inerfield, Jingbo Wang
ISSC 2006/VERY HIGH-SPEED ADCs AND DACs
S. Gupta, Teranetics, Santa Clara, CA
VLSI Course Presentation:
Arash Mirhaj
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Outline
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Brief Introduction
What is Time-Interleaving?
State of the art
Impairments of the Time-Interleaved
Introducing two conventional methods Compensating the
impairments
High-Bandwidth scalable Time-Interleaved Architecture
Implementation
Results
References
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ADC
• In every electronic system, Input and Output of the
system have to be Analog whether the processor is
Analog or Digital since the Real World is Analog, so
the necessity of the ADC is obvious.
• As the speed of the processors is increasing, HighSpeed ADC’s are more required.
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ADC Architectures
Fig.1 : Comparison between different ADC architectures (adopted form [6]).
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High-Speed ADCs
• High Speed ADC’s are
mostly implemented in
Pipeline
architectures
and
Accuracy
is
moderate.
SNR(dB)  1.76
ENOB 
6.02
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bits ENOB
Sampling rate
DALLAS
semiconduct
or
(MAX1219)
12
10.8
210MS/s
ANALOG
DEVICES
(AD12401)
12
10.9
250MS/s
CHIP IDEA
(C13413cn)
10
----
150MHz
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Very High-Speed ADCs
• Very High-Speed ADC’s are
implemented
in
TimeInterleaved architecture as
shown here:
SUBADC
SUBADC
SUBADC
Fig 2: Time Interleaving [3]
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Fig 3: Time Interleaved ADC
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State of The Art
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2 GS/s, 6b ADC in 0.18 μm CMOS
– Jiang et. al., UCLA & Broadcom, IS SCC’03
– No interleaving, 5.7 ENOB, 0.5 mm2, 310 mW, 1.8 V
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20 GS/s, 8b ADC in 0.18 μm CMOS
– Poulton et. al., Agilent, IS SCC’03
– Uses interleaving, 4.6-6.5 ENOB, 196 mm2, 9 W
– Requires BiCMOS buffer chip
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What would 1 GS/s at 11 ENOB require?
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Huge sampling capacitors to keep KT/C noise down (~4 pF)
Extremely low jitter sampling clock (~100 fs)
These specifications are not attainable in the near future in
standard digital CMOS processes
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Presented ADC
• A time-interleaved ADC architecture that
eliminates the need to correct timing offsets
and is yet scalable to high sampling rates is
presented. This 1GS/s 11b ADC has 55dB
peak SNDR, consumes 250mW power, and
occupies 3.5mm2 area.
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Impairments of the Time-Interleaved
• Time-interleaved ADCs suffer from gain
mismatch, offset and timing mismatch errors
between the individual sub-sampled ADCs
(Sub-ADCs).
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Offset Mismatch
• Consider 2-channel Time-Interleaved ADC having
only the Offset impairment (ideal channel 1 and nonideal channel 2) and input signal in Zero:
t
Channel 1
Channel 2
• As can be seen this error can generate a signal with
Non-Zero frequency even if the input signal is DC or
Zero
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Gain Mismatch
• Now assume that 2-channel Time-Interleaved ADC has only
Gain Mismatch between Sub-ADCs (ideal channel 1 and nonideal channel 2) and input signal in DC:
Input
Channel 1
Channel 2
t
• As can be seen this error can generate a signal with
Non-Zero frequency even if the input signal is DC.
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Timing Mismatch
• Now assume that 2-channel Time-Interleaved ADC has only
Timing Mismatch between Sub-ADCs (ideal channel 1 and
non-ideal channel 2) and input signal is a single tone sinusoid:
Channel 1
t
Channel 2
Ideal
Channel 2
• It is obvious that Timing Error can produce many other
frequencies even if a single tone input is fed to the ADC.
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Solutions
• Gain and offset errors can be corrected using
traditional techniques [2, 3, 4].
• However, timing errors are harder to
compensate and lead to a more stringent
limitation on time-interleaved architectures.
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A Digital Background Calibration [2]
1. Random Chopper-Based Offset Calibration
Fig. 4: Digital background offset cancellation [3]
2. Gain Calibration
Fig. 5: Digital background Gain cancellatio [3]
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An Analog Background Calibration
Technique [3]
• Three high-speed time-interleaved ADC’s are used. At any time, two of the
three high-speed ADC’s operate in a ping-pong mode, allowing a dataconversion rate that is double that of each individual ADC. Meanwhile, the
other ADC is selected to be in a calibration mode. In the calibration mode,
the selected ADC and the reference ADC are fed identical inputs for many
conversions, and the gain and offset of the selected ADC is adjusted to
match that of the reference ADC.
Fig. 6: An Analog Background Calibration Technique [4]
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Conventional Time Interleaving [2]
• In a first conventional time-interleaved architecture, an input S/H which
operates at the maximum sampling rate (Fs) of the ADC is employed. The
signal at the output of the S/H is held during the off time of this clock. If the
Sub-ADC samples while its input signal is held, the skew in its clocks does
not lead to loss of signal-to-noise-and-distortion ratio (SNDR).
Fig. 7: Conventional Time Interleaving [3]
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Conventional Time Interleaving [2]
• Thus, the S/H effectively solves the degradation in
SNDR due to phase skew in the Sub-ADC clocks.
The disadvantage is that for N Sub-ADCs, at least
N/2 Sub-ADCs load the S/H.
• Because the loading on the S/H is directly dependent
on the amount of interleaving, the use of this
architecture is limited for large interleaving factors.
• In addition, the Sub-ADC input signal is held for a
short time as the S/H output is at the maximum
sampling rate, which makes the design of the input
sampling network of the Sub-ADC difficult.
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Conventional Time Interleaving [3]
• In a second conventional architecture, a high speed
S/H is not used. Each Sub-ADC has its own subsampled S/H (Sub-S/H). This architecture is more
scalable to high sampling rates, but the phase skew
between different Sub-S/H clocks contributes to loss
of SNR.
Fig. 8: Conventional Time Interleaving [4]
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Conventional Time Interleaving [3]
• To solve this problem, DSP techniques have been
suggested in [6], but have limitations for broadband
input signals. Other time-interleaved ADCs using this
architecture have used timing calibration [7] where
accurate test signal generation, complexity of
hardware implementation, and residual misalignment
left after calibration are additional limitations.
• Finally, despite the removal of the high-speed S/H, a
pre-driver is still required to drive the array of SubS/Hs, which can consume large power for high
accuracy.
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HIGH-BANDWIDTH SCALABLE TIMEINTERLEAVED ARCHITECTURE [1]
• The first sampling is done at fs
through a switch followed by
an array of Sub-S/H circuits. A
timing technique and a
sampling network is devised
such that it achieves the
following three functions
thereby
mitigating
the
disadvantages of the prior two
architectures and resulting in a
low-power design.
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Fig. 9: Improved Time-Interleaved ADC [1]
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HIGH-BANDWIDTH SCALABLE TIMEINTERLEAVED ARCHITECTURE [1]
• Double sampling
• No bottom-plate sampling
Fig. 9: Improved Time-Interleaved ADC and its timing [1]
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HIGH-BANDWIDTH SCALABLE TIMEINTERLEAVED ARCHITECTURE [1]
1.
2.
3.
No more than one of the Sub-S/Hs loads the first sampling
switch for any appreciable time, thereby its achievable
bandwidth and linearity is not limited.
To ensure that timing mismatch in Sub-S/Hs does not limit
the SNR, the turn-off of the clock performing the sampling
in the Sub-S/Hs is done during the off phase of the first
sampling switch. Based on the above two functions, the onperiod of the Sub-S/Hs sampling is kept lower than T.
Double sampling is used to maximally utilize the power of
amplifiers in the ADC in both of the phases of the subsampled clock. This architecture thus requires only N/2 SubS/Hs and Sub-ADCs having two sub-sampled clocks each,
at a frequency of fs/N, and results in reduced total power.
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Bottom-Plate Sampling
Φin
Analog
Input
ΦCH
C
+ Sampled
Voltage
Φb
Fig. 10: Bottom-Plate sampling
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Implementation
• The Sub-ADC is implemented using 11b pipelined
converters to keep the contribution of quantization
noise negligible as compared to the device noise, for
a SNR specification of ~58dB.
• The pipelined architecture is a three-stage design
resolving 3.5 bits in the first two stages and 5 bits in
the last stage. Multi-bit design improves the SFDR
for a given total capacitor value in the MDAC [8].
• Thus, the sampling capacitor value is limited by kT/C
noise requirements, rather than matching.
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Test Results
• For test purposes, the gain and offset error correction
is done in software.
• The ADC is implemented in a 0.13μm 1.2V/2.5V
logic CMOS process. The peak SNR is 58.6dB and
the peak SNDR is 55dB. The ADC has 52dB SNDR
at 400MHz input frequency. The conversion
efficiency, defined by power/(2ENOB.2.ERBW) is
better than 0.5pJ/conversion-step. This ADC has the
highest SNDR, SNR and linearity for any reported
ADC sampling >500MS/s, and the lowest reported
power for any ADC comparable to its accuracy and
speed.
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Test Results
• Effect of Offset and Gain correction
Fig. 11: FFT at 5MHz input with and without gain and offset correction [2]
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Two-Tone FFT
Fig. 12: FFT for two-tone input at 470 and 471 MHz, IMD3<-53dB [2].
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INL/DNL
Fig. 13: DNL and INL [2]
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SNR/SNDR
Fig. 14: SNR/SNDR Vs Input Freq/Input Power [2]
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Chip Micrograph
Fig. 15: Chip Micrograph [1]
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Conclusions
• Proposed Time-Interleaved ADC solved the
timing mismatch error in a very simple way.
• New timing scheme, loads the input with only
one cannel.
• So higher frequencies can be reached.
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References
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[1] S. Gupta, M. Choi, M. Inerfield, and J. Wang, “A 1 GS/s 11b timeinterleaved ADC in 0.13-mCMOS,” in
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 576–577.
[2] S. Gupta, M. Choi, M. Inerfield, and J. Wang, “A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW
Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture” in IEEE JOURNAL OF
SOLID-STATE CIRCUITS, VOL. 41, NO. 12, DECEMBER 2006 pp-2650-2657
[3] S. Jamal et al., “A 10-b 120-Msample/s Time-Interleaved Analog-to-Digital Converter with Digital
Background Calibration,” IEEE J. Solid-State Circuits, vol 37, no. 12, pp. 1618-1627, Dec. 2002.
[4] K. Dyer et al., “An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital
Converters,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1904-1911, Dec., 1998.
[5] K. Poulton et al., “A 20GS/s 8b ADC with a 1MB Memory in 0.18μm CMOS”, ISSCC Dig. Tech.
Papers, pp. 318-319, Feb., 2003
[6] William C. KUN “Introduction to D/A and A/D Converters” MICHIGAN STATE UNIVERSITY OCT.
27Th 2004.
[7] S. M. Jamal, D. Fu, N. C.-J. Chang, P. J. Hurst, and S. H. Lewis, “A 10-bit 120-Msample/s timeinterleaved analog-to-digital converter with digital background calibration,” IEEE J. Solid-State Circuits,
vol. 37, no. 12, pp. 1618–1627, Dec. 2002.
[8] K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A.
Montijo, “A 20 GS/s 8b ADC with a 1 MB memory in 0.18 um CMOS,” in IEEE Int. Solid-State Circuits
Conf. Dig. Tech. Papers, Feb. 2003, pp. 318–319.
[9] W. Yang et al., “A 3-V 340mW 14-b 75-MSample/s CMOS ADC with 85- dB SFDR at Nyquist Input”,
IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1931-1936, Dec. 2001.
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Thank You
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