Transcript Exceptions

Extensions to the Multicycle CPU
Additional Instructions
Exceptions
addi
• No new circuits needed
• third state (after instruction decode) is the
same as for lw/sw
– add the register and the sign-extended immediate
• fourth state is similar to R-type write-back
– but RegDst must be 0
– call this new state 10
bne
• branch off zero line with a not
• combine this line with the zero line in a MUX
– send result to AND gate with PCWriteCond
– control with new control line called bne
• 0 to select beq, 1 to select bne
• FSM needs a new state similar to Branch
completion
– add the control bne = 1, call this state 11
– in the existing branch completion, set bne = 0
PCWriteCond
PCWrite
PCSrc
31-26
Control
25-0
Shift
Left
2
PC 31-28
1
0
MemWrite
IorD
P
C
Zero
MemRead
ALUSrcA
IRWrite
0
1
0
1
2
bne
RegDst
0
25-21
Read/Write
Addr
Memory
Read Reg 1
Read
Read Reg 2Data 1
20-16
IR
0
15-11
Mem
Data
Reg
A
1
Registers
Write Reg
Mem Data
Write Data
RegWrite
1
Read
Data 2
B
4
Write Data
0
0
1
2
3
A
L
U
ALU
Out
ALUSrcB
1
15-0
MemtoReg
Sign
Ext
5-0
Shift
Left
2
ALU
Ctrl
ALUOp
Finite State Machine with addi, bne
Instruction
Fetch 0
Instruction
Decode 1
MemRead
IorD = 0
IRWrite
ALUSrcA = 0
ALUSrcB = 01
ALUOp = 00
PCSrc = 00
PCWrite
Start
Memory ALUSrcA = 1
Address ALUSrcB = 10
Comp 2 ALUOp = 00
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
lw or sw or addi
R-type
bne
addi
Memory
Access
MemRead
lw 3
IorD = 1
sw
Write RegDst = 0
Back
RegWrite
10 MemtoReg = 0
Memory
MemWrite
Access
IorD = 1
sw 5
Write
Back
4
RegWrite
MemToReg = 1
RegDst = 0
beq
Execution ALUSrcA = 1
6
ALUSrcB = 00
ALUOp = 10
lw
j
Write RegDst = 1
RegWrite
Back
7 MemtoReg = 0
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSrc = 01
bne = 1
Branch
Completion
11
Jump
Completion
9
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSrc = 01
bne = 0
Branch
Completion
8
PCWrite
PCSrc = 10
Exceptions
• Unexpected or Unscheduled event which
causes a change in the flow of instructions
• Examples:
– Internal
• Non-existent opcode
• Integer overflow
• Program request to operating system
– External Interrupt
• I/O request
• Hardware malfunction
• Requires change in instruction sequence
Exception Handling - Multicycle
• Detection and Cause
–
–
–
–
non-existent opcode -- control
overflow
-- signal from ALU
I/O request
-- external signal
set register to record cause
• Save location in program (address of current
instruction)
– register (EPC), needed
• Change control to exception handling code
– enter address of exception code into PC
Exception Circuitry - Multicycle
• Overflow signal to control
– to detect overflow
• Register to save address of current instruction
– EPC (Exception Program Counter)
• Register to record the cause of the exception
– As many bits as needed to record the different types
of exception
– 32 bits in MIPS, but not all bits are used
– Called Cause register
• Address of exception code through MUX to PC
– Selected by PCSrc, choice 11
CauseWrite
PCWriteCond
PCWrite
PCSrc
Control
MemWrite
MemRead
IorD
P
C
31-26
25-0
1
0
ALUSrcA
IRWrite
Read/Write
Addr
0
Read Reg 1
Read
Read RegData
2 1
20-16
IR
0
Mem Data
Register
s Read
Write Reg
Data 2
1
15-11
Write Data
Me
m
Data
Reg
EPCWrite
RegDst RegWrite
25-21
Memory
C0000000
PC 31-28
0
1
2
3
4
Zero
0
1
Shift
Left
2
bne
A
B
1
4
Write Data
0
0
1
2
3
Overflow
A
L
U
ALU
Out
IntCause
ALUSrcB
1
15-0
MemtoReg
EPC
Sign
Ext
5-0
Shift
Left
2
ALU
Ctrl
ALUOp
0
0
1
1
C
a
u
s
e
Finite State Machine with exceptions
13
0
Start
1
Instruction
Decode/
Register
Fetch
Instruction
Fetch
lw or sw or addi
other Ops
R-type
Mem
2 Addr Comp
bne
or Addi
Exe
addi
lw
3
sw
10
Mem
Access
lw
5
Mem
Access
sw
Write-back
addi
7
9
Write-back
R-Type
11
Overflow
12
jump
completion
bne
completion
4
Write-back
beq
R-Type
Execute
6
rfe
j
ALUOp = 01
ALUSrcA = 0;
ALUSrcB = 01
IntCause = 0; CauseWrite
EPCWrite; PCWrite
PCSrc = 11
ALUOp = 01
ALUSrcA = 0; ALUSrcB = 01
IntCause = 1; CauseWrite
EPCWrite; PCWrite
PCSrc = 11
beq
completion
8
PCWrite
PCSrc = 100
14
Exception Code
• Located a fixed memory location
– 0xC0000000
• Must first save state (as with any function call)
– At end must restore state
• Decodes Cause Register to determine type of
exception
– branches to appropriate code
• Some exceptions cause program to be aborted
– print appropriate error message
Exception Code
• Some exceptions take an action
– run code to handle input from disk/keyboard/mouse
– run code to handle output to screen/other device
• The return control to previous program
– restore state
– rfe (return from exception)
• put the address held in the EPC back into the PC
• previous program continues from point where it was
interrupted