Transcript Chapter Five

Where we are headed
•
•
Single Cycle Problems:
– what if we had a more complicated instruction like floating point?
– wasteful of area
One Solution:
– use a “smaller” cycle time
– have different instructions take different numbers of cycles
– a “multicycle” datapath:
Instruction
register
PC
Address
Data
A
Memory
Data
Register #
Instruction
or data
ALU
Registers
Memory
data
register
ALUOut
Register #
B
Register #
1
Multicycle Approach
•
•
•
We will be reusing functional units
– ALU used to compute address and to increment PC
– Memory used for instruction and data
Our control signals will not be determined solely by instruction
– e.g., what should the ALU do for a “subtract” instruction?
We’ll use a finite state machine for control
2
Review: finite state machines
•
Finite state machines:
– a set of states and
– next state function (determined by current state and the input)
– output function (determined by current state and possibly input)
Current state
Next-state
function
Next
state
Clock
Inputs
Output
function
Outputs
– We’ll use a Moore machine (output based only on current state)
3
Review: finite state machines
•
Example:
B. 21 A friend would like you to build an “electronic eye” for use as a fake security
device. The device consists of three lights lined up in a row, controlled by the outputs
Left, Middle, and Right, which, if asserted, indicate that a light should be on. Only one
light is on at a time, and the light “moves” from left to right and then from right to left,
thus scaring away thieves who believe that the device is monitoring their activity. Draw
the graphical representation for the finite state machine used to specify the electronic eye.
Note that the rate of the eye’s movement will be controlled by the clock speed (which
should not be too great) and that there are essentially no inputs.
4
Multicycle Approach
•
•
Break up the instructions into steps, each step takes a cycle
– balance the amount of work to be done
– restrict each cycle to use only one major functional unit
At the end of a cycle
– store values for use in later cycles (easiest thing to do)
– introduce additional “internal” registers
PC
0
M
u
x
1
Address
Memory
Instruction
[25– 21]
Read
register 1
Instruction
[20– 16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
MemData
Instruction
[15– 0]
Write
data
Instruction
register
Instruction
[15– 0]
Memory
data
register
0
M
Instruction u
x
[15– 11]
1
A
B
0
M
u
x
1
Sign
extend
32
Zero
ALU ALU
result
ALUOut
0
4
Write
data
16
0
M
u
x
1
1 M
u
2 x
3
Shift
left 2
5
Multicycle Datapath with control signals
I o rD
PC
M e m R e ad
M e m W r ite
IR W r it e
R eg D st
R e g W r it e
A L U S rc A
0
0
In s t ru c tio n
M
u
Read
[2 5 – 2 1 ]
A d dre ss
M
r e g is t e r 1
u
x
R ead
M e m o ry
1
In s t ru c tio n
Read
[2 0 – 1 6 ]
d a ta
I n s tru c t io n
R e g is te rs
W rite
Read
M
I n s tru c tio n
[1 5– 1 1]
r e g is t e r
u
x
In s tr u c tio n
[1 5 – 0 ]
ALU
A LU O ut
res ult
B
d a ta 2
0
4
W rite
1
re g is te r
Z e ro
1
ALU
0
In s t ru c tio n
[1 5 – 0 ]
da ta 1
r e g is t e r 2
M e m D a ta
W r ite
x
A
d a ta
0
1 M
u
2 x
3
M
u
x
M e m o ry
d a ta
1
16
32
S ig n
r e g is te r
ex ten d
S h if t
le ft 2
ALU
c o n t ro l
I n s tru c t io n [5 – 0 ]
M e m to R e g
A L U S rcB AL U O p
6
Multicycle Datapath & Control
PCWriteCond
PCSource
PCWrite
ALUOp
IorD Outputs
ALUSrcB
MemRead
ALUSrcA
Control
MemWrite
RegWrite
MemtoReg
Op
RegDst
IRWrite
[5– 0]
0
M
26
Instruction [25– 0]
PC
0
M
u
x
1
Shift
left 2
Instruction
[31-26]
Address
Memory
MemData
Write
data
Instruction
[25– 21]
Read
register 1
Instruction
[20– 16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Write
data
Instruction
[15– 0]
Instruction
register
Instruction
[15– 0]
Memory
data
register
0
M
Instruction u
x
[15– 11]
1
B
4
0
M
u
x
1
16
Sign
extend
32
Shift
left 2
1 u
x
2
PC [31-28]
0
M
u
x
1
A
28
Jump
address [31-0]
Zero
ALU ALU
result
ALUOut
0
1 M
u
2 x
3
ALU
control
Instruction [5– 0]
7
Five Execution Steps
•
Instruction Fetch
•
Instruction Decode and Register Fetch
•
Execution, Memory Address Computation, or Branch Completion
•
Memory Access or R-type instruction completion
•
Write-back step
INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!
8
High level view of finite state machine control
Start
Instruction fetch/decode and register fetch
(Figure 5.37)
Memory access
instructions
i r .
R-type instructions
( i
. )
Branch instruction
(Figure . 0)
Jump instruction
( i r .
9
Step 1: Instruction Fetch
•
•
•
Use PC to get instruction and put it in the Instruction Register.
Increment the PC by 4 and put the result back in the PC.
Can be described succinctly using RTL "Register-Transfer Language"
IR = Memory[PC];
PC = PC + 4;
Can we figure out the values of the control signals?
What is the advantage of updating the PC now?
10
Step 2: Instruction Decode and Register Fetch
•
•
•
Read registers rs and rt in case we need them
Compute the branch address in case the instruction is a branch
RTL:
A = Reg[IR[25-21]];
B = Reg[IR[20-16]];
ALUOut = PC + (sign-extend(IR[15-0]) << 2);
•
We aren't setting any control lines based on the instruction type
(we are busy "decoding" it in our control logic)
11
Instruction Fetch & Decode
Instruction decode/
Register fetch
Instruction fetch
0
1
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
(Op = 'JMP')
Start
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
PCWrite
PCSource = 00
Memory reference FSM
(Figure 5.33)
R-type FSM
(Figure 5.34)
Branch FSM
(Figure 5.35)
Jump FSM
(Figure 5. 36
)
12
Step 3 (instruction dependent)
•
ALU is performing one of three functions, based on instruction type
•
Memory Reference:
ALUOut = A + sign-extend(IR[15-0]);
•
R-type:
ALUOut = A op B;
•
Branch:
if (A==B) PC = ALUOut;
13
Step 4 (R-type or memory-access)
•
Loads and stores access memory
MDR = Memory[ALUOut];
or
Memory[ALUOut] = B;
•
R-type instructions finish
Reg[IR[15-11]] = ALUOut;
The write actually takes place at the end of the cycle on the edge
14
Write-back step
• Reg[IR[20-16]]= MDR;
What about all the other instructions?
15
Finite state machine for memory access
instructions
From state 1
(Op = 'LW') or (Op = 'SW')
Memory address computation
2
(Op = 'LW')
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
Memory
access
3
Memory
access
5
MemRead
IorD = 1
MemWrite
IorD = 1
Write-back step
4
RegWrite
MemtoReg = 1
RegDst = 0
To state 0
(Figure 5.32)
16
Finite state machine for R-format instructions
From state 1
(Op = R-type)
Execution
6
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
R-type completion
7
RegDst = 1
RegWrite
MemtoReg = 0
To state 0
(Figure 5.32)
17
Finite state machine for branch instruction
From state 1
(Op = 'BEQ')
Branch completion
8
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSource = 01
To state 0
(Figure 5.32)
18
Finite State Machine for jump
From state 1
(Op = 'J')
Jump completion
9
PCWrite
PCSource = 10
To state 0
(Figure 5.32)
19
Summary:
Step name
Instruction fetch
Action for R-type
instructions
Instruction
decode/register fetch
Action for memory-reference
Action for
instructions
branches
IR = Memory[PC]
PC = PC + 4
A = Reg [IR[25-21]]
B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
Execution, address
computation, branch/
jump completion
ALUOut = A op B
ALUOut = A + sign-extend
(IR[15-0])
Memory access or R-type
completion
Reg [IR[15-11]] =
ALUOut
Load: MDR = Memory[ALUOut]
or
Store: Memory [ALUOut] = B
Memory read completion
if (A ==B) then
PC = ALUOut
Action for
jumps
PC = PC [31-28] II
(IR[25-0]<<2)
Load: Reg[IR[20-16]] = MDR
20
Complete Finite State Machine
Instruction decode/
register fetch
Instruction fetch
Start
Memory address
computation
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
PCWrite
PC Source = 00
6
ALUSrcA = 1
ALUSrcB = 10
ALUOp = 00
(Op = 'LW')
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
Branch
completion
Execution
2
8
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
Memory
access
3
1
Memory
access
5
MemRead
IorD = 1
(Op = 'J')
0
Jump
completion
9
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PC WriteCond
PCSource = 01
PCWrite
PC Source = 10
R-type completion
7
MemWrite
IorD = 1
RegDst = 1
RegWrite
MemtoReg = 0
Write-back step
4
R egDst = 0
RegWrite
MemtoReg = 1
21
Simple Questions
•
How many cycles will it take to execute this code?
Label:
•
•
lw $t2, 0($t3)
lw $t3, 4($t3)
beq $t2, $t3, Label
add $t5, $t2, $t3
sw $t5, 8($t3)
...
#assume not
What is going on during the 8th cycle of execution?
In what cycle does the actual addition of $t2 and $t3 takes place?
22
Exceptions
•
Hardest part of control is to implement exceptions & interrupts
Type of event
From where?
MIPS terminology
I/O device request
External
Interrupt
Invoke the operating
system from user
program
Internal
Exception
Arithmetic overflow
Internal
Exception
Using an undefined
instruction
Internal
Exception
Hardware
malfunctions
Internal or
External
Exception or
interrupt
23
How are exceptions handled?
•
•
In our design, we will consider two types of exceptions
– Arithmetic overflow
– Execution of an undefined instruction
Actions on exception
– Save address of offending instruction in the Exception Program
Counter (EPC)
– Transfer control to the operating system at a pre-specified
address (exception handler)
• OS then takes appropriate action
24
Exception handling
•
•
•
For the OS to take appropriate action, it must know the reason for the
exception
Two ways to communicate reason to OS
– Have a Status register which holds a field that indicates the
reason for the exception
– Vectored interrupts
• Address to which control is transferred depends upon the cause of the
exception
MIPS uses first method above; it has a register called Cause (in
addition to the EPC register)
25
Datapath & Control with support for exceptions
CauseWrite
IntCause
EPCWrite
PCSource
ALUOp
PCWriteCond
PCWrite
IorD
Outputs
MemRead
MemWrite
ALUSrcB
Control
ALUSrcA
MemtoReg
IRWrite
RegWrite
Op
[5– 0]
RegDst
0
26
Instruction [25– 0]
PC
0
M
u
x
1
Shift
left 2
Instruction
[31-26]
Address
Memory
MemData
Read
register 1
Instruction
[20– 16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Write
data
Instruction
register
Instruction
[15– 0]
Memory
data
register
0
M
Instruction u
x
[15– 11]
1
B
4
Write
data
0
M
u
x
1
Zero
ALU ALU
result
Sign
extend
32
Shift
left 2
3
0
1M
u
2 x
3
ALUOut
0
1
16
u
x
PC [31-28]
0
M
u
x
1
A
1M
2
CO 00 00 00
Instruction
[25– 21]
Instruction
[15– 0]
28
Jump
address [31-0]
EPC
0
M
u
x
1
Cause
ALU
control
Instruction [5– 0]
26
Exception Handling
•
•
•
Datapath additions
– EPC, Cause (for undefined instruction, Cause = 0, arithmetic
overflow Cause = 1)
Control Signals
– EPCWrite, CauseWrite
– IntCause (sets the Cause register)
– PCSrc has to be modified so that one of its sources is the OS
entry point
Three steps
1. Write Cause
2. EPC = PC – 4 (Have to use ALU, so need to expand multiplexors
for ALUSrcA and ALUSrcB
3. Write PC
27
Datapath & Control with support for exceptions
CauseWrite
IntCause
EPCWrite
PCSource
ALUOp
PCWriteCond
PCWrite
IorD
Outputs
MemRead
MemWrite
ALUSrcB
Control
ALUSrcA
MemtoReg
IRWrite
RegWrite
Op
[5– 0]
RegDst
0
26
Instruction [25– 0]
PC
0
M
u
x
1
Shift
left 2
Instruction
[31-26]
Address
Memory
MemData
Read
register 1
Instruction
[20– 16]
Read
Read
register 2 data 1
Registers
Write
Read
register data 2
Write
data
Instruction
register
Instruction
[15– 0]
Memory
data
register
0
M
Instruction u
x
[15– 11]
1
B
4
Write
data
0
M
u
x
1
Zero
ALU ALU
result
Sign
extend
32
Shift
left 2
3
0
1M
u
2 x
3
ALUOut
0
1
16
u
x
PC [31-28]
0
M
u
x
1
A
1M
2
CO 00 00 00
Instruction
[25– 21]
Instruction
[15– 0]
28
Jump
address [31-0]
EPC
0
M
u
x
1
Cause
ALU
control
Instruction [5– 0]
28
States for handling exceptions
11
10
IntCause = 0
CauseWrite
ALUSrcA = 0
ALUSrcB = 01
ALUOp = 01
EPCWrite
PCWrite
PC++Source = 11
IntCause = 1
CauseWrite
ALUSrcA = 0
ALUSrcB = 01
ALUOp = 01
EPCWrite
PCWrite
PCSource = 11
PCSource = 11
To state 0 to begin next instruction
29
Complete FSM including support for exceptions
Instruction decode/
Register fetch
Instruction fetch
0
Memory address
computation
6
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 00
(Op = 'LW')
Branch
completion
Execution
2
8
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 10
Memory
access
Memory
access
5
MemRead
IorD = 1
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
ALUSrcA = 1
ALUSrcB = 00
ALUOp = 01
PCWriteCond
PCSource = 01
R-type completion
7
MemWrite
IorD = 1
11
RegDst = 1
RegWrite
MemtoReg = 0
(Op = 'J')
Start
3
1
MemRead
ALUSrcA = 0
IorD = 0
IRWrite
ALUSrcB = 01
ALUOp = 00
PCWrite
PCSource = 00
Overflow
Jump
completion
9
PCWrite
PCSource = 10
IntCause = 1
CauseWrite
ALUSrcA = 0
ALUSrcB = 01
ALUOp = 01
EPCWrite
PCWrite
PCSource = 11
10
IntCause = 0
CauseWrite
ALUSrcA = 0
ALUSrcB = 01
ALUOp = 01
EPCWrite
PCWrite
PCSource = 11
Write-back step
4
Overflow
RegWrite
MemtoReg = 1
RegDst = 0
30
Implementing the Control
•
Value of control signals is dependent upon:
– what instruction is being executed
– which step is being performed
•
Use the information we’ve acculumated to specify a finite state machine
– specify the finite state machine graphically, or
– use microprogramming
•
Implementation can be derived from specification
31
Graphical Specification of FSM
In struction decode/
re gister fetch
Instruction fe tch
Start
M e mory address
com p utation
M em R e ad
AL U SrcA = 0
IorD = 0
IR W rite
AL U SrcB = 0 1
ALU O p = 00
PC W rite
PC Sou rce = 00
6
(Op = 'LW')
A LU SrcA = 1
AL U SrcB = 10
AL U O p = 00
M em ory
access
5
M em R ead
IorD = 1
W rite-bac k step
R eg D st = 0
R eg W rite
M em toR eg = 1
Branch
co m pletion
8
ALU SrcA = 1
A LU SrcB = 00
ALUO p = 10
M em ory
ac ce ss
4
ALU SrcA = 0
AL U SrcB = 11
AL U O p = 00
Exe cution
2
3
1
M em W rite
IorD = 1
Re gD s t = 1
R egW rite
M em toReg = 0
Jum p
com p letio n
9
AL U SrcA = 1
AL U SrcB = 0 0
ALU O p = 0 1
PC W riteCo nd
P C Sou rce = 01
R -type com pletion
7
(Op = 'J')
0
PC W rite
P C S ou rce = 10
Finite State Machine for Control
Implementation:
PCW rite
PCW riteCond
IorD
M em Read
M em W rite
IRW rite
Control logic
M em toReg
PCS ource
ALUO p
Outputs
ALUSrcB
ALUSrcA
RegW rite
RegD st
NS3
NS2
NS1
NS0
Instruction register
opcode field
S0
S1
S2
S3
Op0
Op1
Op2
Op3
Op4
Inputs
Op5
•
State register
33
PLA Implementation
•
If I picked a horizontal or vertical line could you explain it?
Op5
Op4
Op3
Op2
Op1
Op0
S3
S2
S1
S0
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
MemtoReg
PCSource1
PCSource0
ALUOp1
ALUOp0
ALUSrcB1
ALUSrcB0
ALUSrcA
RegWrite
RegDst
NS3
NS2
NS1
NS0
34
ROM Implementation
•
•
ROM = "Read Only Memory"
– values of memory locations are fixed ahead of time
A ROM can be used to implement a truth table
– if the address is m-bits, we can address 2m entries in the ROM.
– our outputs are the bits of data that the address points to.
m
n
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
– m is the "height", and n is the "width"
35
ROM Implementation
•
•
How many inputs are there?
6 bits for opcode, 4 bits for state = 10 address lines
(i.e., 210 = 1024 different addresses)
How many outputs are there?
16 datapath-control outputs, 4 state bits = 20 outputs
•
ROM is 210 x 20 = 20K bits
•
Rather wasteful, since for lots of the entries, the outputs are the
same
— i.e., opcode is often ignored
(and a rather unusual size)
36
ROM vs PLA
•
Break up the table into two parts
— 4 state bits tell you the 16 outputs, 24 x 16 bits of ROM
— 10 bits tell you the 4 next state bits, 210 x 4 bits of ROM
— Total: 4.3K bits of ROM
•
PLA is much smaller
— can share product terms
— only need entries that produce an active output
— can take into account don't cares
•
Size is (#inputs  #product-terms) + (#outputs  #product-terms)
For this example = (10x17)+(20x17) = 460 PLA cells
•
PLA cells usually about the size of a ROM cell (slightly bigger)
37
The Big Picture
Initial
representation
Finite state
diagram
Microprogram
Sequencing
control
Explicit next
state function
Microprogram counter
+ dispatch ROMS
Logic
representation
Logic
equations
Truth
tables
Implementation
technique
Programmable
logic array
Read only
memory
38