Transcript Document

2.7 NAND and NOR logic networks
• Introduce the use of NAND and NOR gates in
the synthesis of logic circuits
– Attractive due to their simpler electronic circuits
implementation than AND and OR functions
– Q: Can be used directly in the synthesis of logic
circuits? And how?
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Graphical symbols for NAND and
NOR gates (Figure 2.20)
x1
x2
x1
x2
x 1  x 2    x n
x 1  x 2
xn
(a) NAND gates
x1
x1
x2
x2
A bubble at the output
side of the gate
symbols
represents the
complemented output
signal.
x 1 + x 2 +  + x n
x1 + x2
xn
(b) NOR gates
2
DeMorgan’s theorem in terms of
logic gates
x1
x2
x1
x2
x1
x2
(a) 𝑥1 𝑥2 = 𝑥1 + 𝑥2
A NAND gate is equivalent to the OR gate with inversions at its inputs.
x1
x2
x1
x2
x1
x2
(b) 𝑥1 + 𝑥2 = 𝑥1 𝑥2
A NOR gate is equivalent to the AND gate with inversions at its inputs
3
x1
x2
x3
x4
x5
Transform a AND-OR networks
into a network of NAND gates
1. Replace each connection
between AND and OR gate
by inversions of signals.
2. Replace OR gate with
inverted inputs by a NAND
gate.
1
x1
x2
x3
x4
x5
2
Double inversion has
no effect on the
network behavior.
x1
x2
x3
x4
x5
Same topology!
Figure 2.22. Using NAND gates to implement a sum-of-products.
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•
x1
x1
x2
x2
x3
x3
x4
x4
x5
x5
Can implement any OR-AND
network as a NOR-NOR
network having the same
topology with the similar
transformation procedure.
x1
x2
x3
x4
x5
Figure 2.23. Using NOR gates to implement a product-of sums.
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Example 2.6
Combining property
14b. (x + y) (x + 𝑦) = x
• Let us implement the function using NOR
gates only
𝑓 𝑥1 , 𝑥2 , 𝑥3 =
𝑚(2, 3, 4 , 6, 7) =
𝑀(0,1,5)
• The POS expression
𝑓 =(x1 + x2 + x3) (x1+x2+𝑥3 )(𝑥1 +x2+𝑥3 )
// apply combining property 14b to
// M0 and M1; M1 and M5
= 𝑥1 + 𝑥2 (𝒙𝟐 + 𝒙𝟑 )
x1
0
0
0
0
1
1
1
1
x2
0
0
1
1
0
0
1
1
x3
0
1
0
1
0
1
0
1
F
0
0
1
1
1
0
1
1
6
x1
x2
f
x3
(a) POS implementation in Example 2.4
x3 is inverted by a NOR
gate that has its inputs x
1
tired together.
𝒙𝟑 = 𝒙𝟑 + 𝒙𝟑
x2
f
x3
(b) NOR implementation
Figure 2.24
NOR-gate realization of the function in Example 2.4.
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Example 2.7
Distributive property
12a. x (y + z) = xy + xz
• Let us implement the function using NAND
x
x
gates only
0
0
1
𝑓 𝑥1 , 𝑥2 , 𝑥3 =
𝑚(2, 3, 4 , 6, 7)
• The SOP expression
𝑓 = 𝑥1 𝑥2𝑥3 + 𝑥1 𝑥2𝑥3 + 𝑥1𝑥2 𝑥3 + 𝑥1𝑥2 𝑥3 + 𝑥1 𝑥2𝑥3
// merge m2, m3, m6, and m7 using P12a;
// merge m4 and m6
= 𝑥2(𝑥1 𝑥3 + 𝑥1 𝑥3 + 𝑥1𝑥3 + 𝑥1𝑥3) + 𝒙𝟏(𝒙𝟐 + 𝒙𝟐 )𝒙𝟑
0
0
0
1
1
1
1
2
0
1
1
0
0
1
1
x3
0
1
0
1
0
1
0
1
F
0
0
1
1
1
0
1
1
All 4 combinations = 1
= x2 + 𝒙𝟏𝒙𝟑
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x2= x2+x2
x2
x2
f
x3
f
x1
x1
x3
(a) SOP implementation
𝒙𝟑 = 𝒙𝟑 ∙ 𝒙𝟑
x2
f
x1
x3
(b) NAND implementation
Figure 2.25. NAND-gate realization of the function in Example 2.3.
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2.8 Design Examples
• Basic issues that a designer is always
confronted with
– Necessary to specify the desired behavior of the
circuit.
– The circuit has to be synthesized and
implemented.
10
Three-way light control
Let x1, x2, and x3 be the input variables
that denote the state of each switch.
Assume that
• the light is off if all switches are
open
• Closing any one of the switches will
turn the light on.
• Closing a second switch will have
to turn off the light, that is to say,
light will be off if two (or no)
switches are closed.
• Turn the light on by closing the third
switch if two switches are closed.
Figure 2.26. Truth table for a three-way light control.
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Canonical SOP and POS
• SOP expression for the specified function
𝑓 = 𝑚1 + 𝑚2 + 𝑚4 + 𝑚7
= 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3
• POS expression for the specified function
𝑓 = 𝑀0𝑀3𝑀5𝑀6
= (𝑥1 + 𝑥2 + 𝑥3) (𝑥1 + 𝑥2 + 𝑥3 )
(𝑥1 + 𝑥2 + 𝑥3 ) (𝑥1 + 𝑥2 + 𝑥3)
12
f
x1
x2
x3
(a) Sum-of-products realization
x1 x2
x3 f1
f2 f3
f4
f
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
0
0
1
0
0
1
1
1
1
1
1
0
1
1
1
0
1
0
1
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
x3
x2
x1
f1
f2
f
f3
f4
(a) Product-of-sums realization
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Multiplexer
Distributive property
12a. x (y + z) = xy + xz
• A circuit that generates an output that exactly
reflects the state of one of a number of data
inputs, based on the value of one or more
selection control inputs.
s x1 x2
f (s, x1, x2)
000
0
001
0
010
1
011
1
100
0
101
1
110
0
111
1
f(s, x1, x2)
= 𝒔𝒙𝟏𝒙𝟐 + 𝒔𝒙𝟏𝒙𝟐 + 𝒔𝒙𝟏𝒙𝟐 + 𝒔𝒙𝟏𝒙𝟐 //12a
= 𝒔𝒙𝟏 𝒙𝟐 + 𝒙𝟐 + 𝒔 𝒙𝟏 + 𝒙𝟏 𝒙𝟐
= 𝒔𝒙𝟏 ∙ 𝟏 + 𝒔 ∙ 𝟏 ∙ 𝒙𝟐
= 𝒔𝒙𝟏 + 𝒔𝒙𝟐
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Implementation of a 2-to-1
multiplexer
= 𝒔𝒙𝟏 + 𝒔𝒙𝟐
x1
s x1 x2
f (s, x1, x2)
000
0
001
0
010
1
011
1
100
0
101
1
110
0
111
1
(a)Truth table
f
s
x2
s
(b) Circuit
f (s, x1, x2)
0
x1
1
x2
s
x1
0
x2
1
(d) More compact truth-table
representation
f
(c) Graphical symbol
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More about complex multiplexer
• A 4-to-1 multiplexer has four data inputs and
one output
– Two selection control inputs are needed
• A 8-to-1 multiplexer needs eight data inputs
and three selection control inputs
• Same circuit structure can be used to
implement multiplexer using NAND gates.
• More discussions on multiplexer are in
Chapter 3 and 6.
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2.12 EXAMPLES OF SOLVED
PROBLEMS
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Example 2.8
Determine if the following equation is valid
𝑥1 𝑥3 + 𝑥2𝑥3 + 𝑥1𝑥2 = 𝑥1 𝑥2 + 𝑥1𝑥3 + 𝑥2 𝑥3
Solution: Derive a canonical SOP form for each expression
(an algebraic approach)
LHS = 𝑥1 (𝑥2 + 𝑥2 )𝑥3 + (𝑥1 + 𝑥1 )𝑥2𝑥3 + 𝑥1𝑥2 (𝑥3 + 𝑥3 )
= 𝑥1 𝑥2𝑥3 + 𝑥1 𝑥2 𝑥3 + 𝑥1𝑥2𝑥3 + 𝑥1 𝑥2𝑥3 + 𝑥1𝑥2 𝑥3 + 𝑥1𝑥2 𝑥3
(
2
0
7
3
5
4 )
= 𝑚(2,0,7,3,5,4) = 𝑚(0,2,3,4,5,7)
RHS = 𝑥1 𝑥2(𝑥3 + 𝑥3 ) + 𝑥1(𝑥2 + 𝑥2 )𝑥3 + (𝑥1 + 𝑥1 ) 𝑥2 𝑥3
= 𝑥1 𝑥2𝑥3 + 𝑥1 𝑥2𝑥3 + 𝑥1𝑥2𝑥3 + 𝑥1𝑥2 𝑥3 + 𝑥1𝑥2 𝑥3 + 𝑥1 𝑥2 𝑥3
= 𝑚(3,2,7,5,4,0) = 𝑚(0,2,3,4,5,7)
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Example 2.9
Combining property
14b. (x + y) (x + 𝑦) = x
Determine the minimum-cost POS expression for the function
f(x1,x2,x3,x4) = 𝑚(0,2,4,5,6,7,8,10,12,14,15)
Solution: To find a POS expression we should start with the
definition in terms of maxiterms, which is f = 𝑀(1,3,9,11,13)
f = M1 ∙ 𝑀3 ∙ 𝑀9 ∙ 𝑀11 ∙ 𝑀13
= (x1+x2+x3+𝒙𝟒 ) (x1+x2+𝒙𝟑 +𝒙𝟒 ) (𝒙𝟏 +x2+x3+𝒙𝟒 )
(𝒙𝟏 +x2+𝒙𝟑 +𝒙𝟒 ) (𝒙𝟏 +𝒙𝟐 +x3+𝒙𝟒 )
M1 ∙ 𝑀3 = x1 + x2 + 𝒙𝟒 // combining property 14b
M9 ∙ 𝑀11= 𝒙𝟏 + x2 + 𝒙𝟒
M9 ∙ 𝑀13= 𝒙𝟏 + x3 + 𝒙𝟒
f = (x1+x2+𝒙𝟒 ) (𝒙𝟏 +x2+𝒙𝟒 ) (𝑥1 +x3+𝑥4 ) = (x2+𝒙𝟒 ) (𝑥1 +x3+𝑥4 )
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Example 2.12
Absorption
13a. x+xy = x
Combining
14a. xy+x𝑦 = x
Derive the simplest SOP expression for the
function
𝑓 = 𝑥2𝑥3𝑥4 + 𝑥1𝑥3𝑥4 + 𝑥1𝑥2𝑥4
Solution:
f = 𝑥2𝑥3𝑥4 + 𝑥1𝑥3𝑥4 + 𝒙𝟐𝒙𝟒𝒙𝟏 + 𝑥1𝑥2𝑥4 //consensus
= 𝑥2𝑥3𝑥4 + 𝑥1𝑥3𝑥4 + 𝒙𝟏𝒙𝟐𝒙𝟒 + 𝒙𝟏𝒙𝟐𝒙𝟒// combining
= 𝑥2𝑥3𝑥4 + 𝑥1𝑥3𝑥4 + 𝒙𝟏𝒙𝟒
= 𝑥2𝑥3𝑥4 + 𝒙𝟏𝒙𝟑𝒙𝟒 + 𝒙𝟏𝒙𝟒
// absorption
= 𝑥2𝑥3𝑥4 + 𝒙𝟏𝒙𝟒
Consensus
17a. xy +𝑥𝑧 + 𝑦𝑧 = xy+𝑥𝑧
20
Problem 2.31
1
0
0
0
0
0
1
1
1
1
x2 1
0
0
0
1
1
0
0
1
1
x3 1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
x1
f
Time
Figure P2.3. A timing diagram representing a logic function.
Synthesize the function in the simplest SOP form
21
Problem 2.31
1
0
0
0
0
0
1
1
1
1
x2 1
0
0
0
1
1
0
0
1
1
x3 1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
x1
f
x1
0
0
0
0
1
1
1
1
x2
0
0
1
1
0
0
1
1
x3
0
1
0
1
0
1
0
1
f
1
0
0
1
0
1
1
0
Time
The simplest SOP expression is
𝑓 = 𝑥1 𝑥2 𝑥3 + 𝑥1 x2x3 + x1𝑥2 x3+x1x2𝑥3
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