Transcript [Week 5] Chap 6. Memory and Programmable Logic Devices [강의Download]

Chap 6.
Memory and Programmable Devices
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6.1 Memory & Programmable Logic Device
Definitions

Memory
– a collection of cells capable of storing binary
information
– memory contains electronic circuits for storing &
retrieving info

Digital computer
– consist of three major units
• Processing unit (registers + combinational logic)
• Memory unit
• I/O unit
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6.1 Memory & Programmable Logic Device
Definitions

two types of memories
– RAM (Random-Access Memory)
• can perform both read & write operation
– ROM (Read-Only Memory)
• can perform only the read operation (cannot write)
• the existing information cannot be altered
• a programmable logic device (PLD)
(programming: a H/W procedure that specifies the bits
that are inserted into the H/W configuration of the device)

Programmable Logic Device (PLD)
– ROM, PLA, PAL, CPLD, & FPGA
– IC with internal logic gates (connected by a programmable process)
• initial state: all the fuses are intact
• programming by blowing those fuses along the paths
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6.2 Random-Access Memory (RAM)
– memory cells can be accessed for information
transfer to (or from) any desired random location
– with access taking the same time regardless of the
location
 random-access memory
(cf) serial memory: magnetic disk, tape
– word : binary information in groups of bits in a
memory unit
– byte : a group of 8 bits
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6.2 Random-Access Memory (RAM)
– configuration:
• data input and output lines, address selection lines, & control
lines
– k address lines: specify the particular word
• address range: 0 to 2k-1
• 2k = m (m: total number of words)
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6.2 Random-Access Memory (RAM)
(ex) a memory unit with 1K words of 16 bits each
•
•
•
•
1024 x 2 bytes = 2K bytes
decimal address: 0 ~ 1023
address: 10 bits
data (word): 16 bits
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6.2 Random-Access Memory (RAM)

Steps of Write Operation
1) Apply the binary address to the address lines
2) Apply the data bits to the data input lines
3) Activate the Write input

Steps of Read Operation
1) Apply the binary address to the address lines
2) Activate the Read input
– control lines
• read & write
• memory select (or chip select) & operation (read/write)
Enable 단자
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6.2 Random-Access Memory (RAM)

Timing Waveforms
– operation of the memory unit is controlled by an external
device (CPU)
– CPU is usually synchronized with its own clock pulses
(memory doesn't employ internal clock pulses)
– Access time of a memory read operation
• the maximum time from the application of the address
to the appearance of the data at the Data Output
– Write cycle time
• the maximum time from the application of the address
to the completion to store a word
– CPU must provide the memory control signals to synchronize
its internal clocked operations with read/write operations of
the memory
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6.2 Random-Access Memory (RAM)
Ex) a CPU with a clock frequency of
50MHz
 a period of 20ns for one clock pulse
with a 65ns access time & a 75ns write
cycle time
Addr.가 확정된 후에
Unspecified value
Control input(R/W)이 deactivate후
잠시 addr.과 data line이 stable하도록
A possible change in value
Bus에 데이터 선적
Register로 이동
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6.2 Random-Access Memory (RAM)

Properties of Memory
– Static RAM (SRAM)
• consist of internal latches that store the binary information
• easier to use, shorter read and write cycles
• No refresh is required
– Dynamic RAM (DRAM)
•
•
•
•
store information in the form of electric charges
capacitors are provided inside the chip by MOS transistors
the capacitors must be periodically recharged by refreshing
reduced power consumption, larger storage capacity
– Volatile
• lose stored information when power is turned off
(ex) RAM (static or dynamic)
(cf) non-volatile
(ex) magnetic disk, ROM, Flash Memory etc.
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6.3 RAM Integrated Circuits

Internal Structure
– a RAM chip of m words & n bits per word consists of m x n binary
storage cells, and decoders

static RAM cell
SR latch
– Select = 0, the stored content is held & C=0 & C'=0
Select = 1, the stored content is determined by B & B',
– C is the stored value & C' is its complement
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6.3 RAM Integrated Circuits

RAM Bit Slice Model
Read occurs
regardless of the value of Read/Write
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6.3 RAM Integrated Circuits

16 x 1 RAM Chip
4 address inputs for the 16
one-bit words
Signals
Data Input,
Data Output,
Read/Write,
Chip Select
4-to-16 line decoder
3-state buffer
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6.3 RAM Integrated Circuits

Three-state Buffer
– have three distinct states
• logic-0, logic-1, high-impedance (Hi-Z) state
• Hi-Z state: open circuit,
(the output appears to be disconnected)
– ENABLE input (EN)
Three-state Buffer
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6.3 RAM Integrated Circuits
– Form a multiplexed output line
Conflict!
• truth table (in shaded area) is a 2-way multiplexer with S
• EN중 하나만 activate
– Decoder와 연결하여 N-to-1 MUX의 기능 구현
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6.3 RAM Integrated Circuits

Problems
– Size of Decoder: k*2k
• 2k : the number of AND
– Access time and write cycle time: can be too long

Coincident Selection
– A decoder with k inputs & 2k outputs requires 2k AND gates with k
inputs per gate
– employ 2 decoders to reduce the total number of gates
 Coincident Selection'
– use 2 k/2-input decoders instead of 1 k-input decoder
• one controls the word select lines,
• the other controls the bit select lines
 two dimensional matrix selection scheme
Row select & Column select
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6.3 RAM Integrated Circuits

16 x 1 RAM chip
4 RAM bit slice of 4
bits each (total 16
RAM cells)
two 2-to-4 line
decoders
one for 2 MSBs
one for 2 LSBs
A3 A2 A1 A 0
1 0 0 1
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6.3 RAM Integrated Circuits
Cf) 8 x 2 RAM chip
: 8 words of 2 bits each
• 3 address bits
– two are handled
by the row decoder
– column decoder has only
one address bit &
produces 2 column select
lines
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6.3 RAM Integrated Circuits
Ex) 32K x 8 RAM (= 215 x 8)
– a total of 256K bits (= 218)
– square root of 256K is 29
• first 9 bits fed to the row decoder
• remaining 6 bits to the column decoder
– without coincident selection,
the single decoder has 15 inputs & 32,768 outputs
– with coincident selection,
one 9-to-512 decoder and one 6-to-64 line decoder
 Shorter access (write) time
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Dynamic RAM ICs
Switch 역할
B
C
B
1
C
0
Write
Write 1
Write 0
Read
Read 1
Read 0
Destructive read
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Dynamic RAM ICs
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Dynamic RAM ICs
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Dynamic RAM ICs
During the read operation,
All values in the addressed row are restored
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6.4 Array of RAM ICs
– if required memory size is larger than the capacity of one chip,
combine a number of chips in an array
– capacity of memory
• the number of words & the number of bits per word
• When CS=0, the chip is not selected, and all its data outpus are in
the high-impedance state.

64K x 8 RAM chip
– 16 address lines, 8 input & 8 output lines
– CS (chip select), R/W' inputs
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6.4 Array of RAM ICs

Expanding the number of words
– Construct 256K x 8 RAM four
64K x 8 RAM chips
• requires 18-bit address lines
• 2 MSBs are applied to a 2 x 4
decoder,
• 4 outputs are applied to the CS
inputs of the four chips
0 1 xxxx…xxxx
Lines 0-15
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6.4 Array of RAM ICs

Expanding the number of address bits
– Form a 64K x 16 memory
• 16 data input & output lines are split between the two chips
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6.5 Programmable Logic Technologies

Five programmable logic devides (PLDs)
– ROM, PLA, PAL, CPLD, & FPGA

Programming technologies
– fuse
• oldest of the programming technologies
• each of programmable points consists of a connection, formed by a fuse
• 2 connection states, CLOSED & OPEN
– mask programming
• Connections are made or not made in the metal layers serving as conductor in the
chip
• by semiconductor manufacturer
• May be too costly
– antifuse
• the opposite of a fuse
• The material separating the two conductor is melted
– static RAM bit
• drive the gate of an MOS transistor at the programming point
• Electrically programming
– Easy but require power supply
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6.5 Programmable Logic Technologies

Applications of programming technologies
– control connections
– implement logic by building lookup tables
• input: address inputs for reading the SRAM
• output: stored truth values for the addressed word
– control transistor switching
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6.6 Read-Only Memory
– a memory device in which permanent binary info is stored
– once a pattern is established, it stays even when power is off
– consist of k address inputs and n data outputs
– input: address for the memory;
– output: data bits of the stored word, selected by the address
• no data input lines !
– k address input lines are needed to specify 2k words
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6.6 Read-Only Memory
Ex) 32 x 8 ROM
• the unit consists of 32 words of 8 bits each
• 5 x 32 decoder (5 input lines)
• the internal binary storage of a ROM is specified by a truth table
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6.6 Read-Only Memory
Ex) the contents of a 32 x 8 ROM
programming the ROM according to
the truth table
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6.6 Read-Only Memory

Combinational Circuit Implementation
– a decoder generates the 2k minterms of the k input variables
– inserting OR gates to sum the minterms of Boolean functions
 can generate any desired combinational circuit
– ROM essentially includes both decoder & OR gates
– ROM outputs can be programmed to represent the Boolean functions
in a combinational circuit
– ROM may be considered as a comb circuit with (8) outputs,
each is a function of the (5) input variables
A7(I4,I3,I2,I1,I0) =  m(0,2,3,...,29)
– widely used to implement complex combinational circuits directly
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6.6 Read-Only Memory

Types of ROMs
–
–
–
–
mask programming (ROM)
fuse (Programmable ROM, PROM)
erasable floating gate technology (EPROM)
electrically erasable technology (EEPROM, E2PROM)
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6.6 Read-Only Memory
Ex 6.1 Design a comb circuit using a ROM
• accepts a 3-bit number
• Then, generates an output binary number equal to the square of the input number
• 3 inputs & 6 outputs
but B0 = A0; B1 = 1;
 only need 4 outputs
 ROM must be 8 x 4
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Programmable Logic Device

Programmable Logic Device
– An integrated circuit with an array of gates that are connected by
programmable fuses
– The gates in a PLD are divided into AND array & OR array to
provide and AND-OR sum of products implementation
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Programmable Logic Device

PROM
– a fixed AND array constructed as a decoder & programmable
connections for the output OR gates
– implements Boolean functions in sum-of-minterms form

PAL
– a programmable connection AND array & a fixed OR array
– AND gates are programmed to provide the product terms, which are
logically summed in each OR gate

PLA
– most flexible PLD
– both AND & OR arrays can be programmed
– product term in the AND array may be shared by any OR gate
provide the required sum of products implementation
to
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6.7 Programmable Logic Array (PLA)

PLA is similar to the PROM in concept
– But, the PLA doesn't provide full decoding of the
variables & doesn't generate all the minterms
– Decoder is replaced by an array of AND gates
• to generate any product term of the input variables
– Product terms are then connected to OR gates to
provide the sum of products
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6.7 Programmable Logic Array (PLA)
Ex) internal logic of a PLA with 3 inputs & 2
outputs
- Output of OR gates goes to an XOR gate
X0 = X
X1 = X’
F1 = AB' + AC + A'BC'
F2' = AC + BC
programmable
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6.7 Programmable Logic Array (PLA)

the fuse map of a PLA in a tabular form;
– consists of 3 sections
• list of the product terms
• the required paths between inputs & AND gates
• the path between the AND & OR gates
– a careful investigation must be undertaken to reduce the number of distinct
product terms
• Because PLA has a finite number of AND gates
– So, simplify each Boolean function to a minimum number of terms
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6.7 Programmable Logic Array (PLA)
Ex 6.2 Implement the following functions with a PLA
F1(A,B,C) =  m(0,1,2,4);
F2(A,B,C) =  m(0,5,6,7)
1) true & complement of the functions are
simplified in sum of products
2) select a combination that gives a minimum
number of product terms
F1 = (AB +AC +BC)';
F2 = AB + AC + A'B'C'
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6.7 Programmable Logic Array (PLA)

PLA의 크기를 결정하는 인자
– Input 수: n, output 수: m, product term 수: k
•
•
•
•
•
n개의 buffer-inverter gates
k개의 AND gates
m개의 OR gates
m개의 XOR gates
fuze(programmed link)의 개수: 2n x k + k x m + m
– n에 대해서 linear하게 증가
– Cf) ROM에서의 fuze의 개수: 2n x m
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6.8 Programmable Array Logic (PAL)
– PLD with a fixed OR array & programmable
AND array
– easier to program
• only AND gates are programmable
– not flexible as the PLA
– Product terms cannot be shared
– logic configuration of a commercial PAL
• 8 inputs & 8 outputs
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6.8 Programmable Array Logic (PAL)
– 4 section in the unit,
• each composed of a 3-wide AND-OR array
– 3 programmable AND gates in each section
– F/Fs are often included in a PAL device
• outputs of F/F are fed back through a buffer-inverter gate
– sequential circuits
– in designing with a PAL,
• the Boolean functions must be simplified to fit into each section
• a product term cannot be shared
• number of product terms in each section is fixed
– may be necessary to use 2 sections to implement 1 function
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6.8 Programmable Array Logic (PAL)
(Ex) W(A,B,C,D) =  m(2,12,13);
X(A,B,C,D) =  m(7,8,9,10,11,12,13,14,15)
Y(A,B,C,D) =  m(0,2,3,4,5,6,7,8,10,11,15)
Z(A,B,C,D) =  m(1,2,8,12,13)
After simplification
W= ABC' + A'B'CD';
X = A + BCD;
Y = A'B + CD + B'D';
Z = ABC' + A'B'CD' + AC'D' + A'B'C'D
= W + AC'D' + A'B'C'D;
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6.8 Programmable Array Logic (PAL)
- PAL programmable table
W = ABC' + A'B'CD';
X = A + BCD;
Y = A'B + CD + B'D';
Z = ABC' + A'B'CD' + AC'D' + A'B'C'D
= W + AC'D' + A'B'C'D;
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6.9 VLSI Programmable Logic Devices

3 ways of designing VLSI circuits
– Full custom design
• An entire design of chip is performed to the smallest detail of the layout
• For dense, fast ICs that are likely to be sold in sizable quantities
• Very expensive
– Standard cell design
• Large part of the design have been performed ahead of time
• Pre-designed parts are connected to form the IC design
• Give lower density & lower performance than full custom design
– Gate array
• A pattern of gates fabricated in silicon that is repeated thousand times, so that the entire
chip contains identical gates
• Arrays of 1,000 to 1,000,000 of gates can be fabricated within a single IC
• Design specify how the gates are interconnected & the interconnections are routed
• Economical, can be highly automated with CAD
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6.9 VLSI Programmable Logic Devices

CPLDs & FPGAs
– CPLD: Complex Programmable Logic Devices
– FPGA: Field Programmable Gate Array
– Properties
1. Substantial amounts of uncommitted combinational logic
2. Pre-implemented flip-flops
3. Programmable interconnections between the combinational logic, flip-flops, and the
chip input/outputs
–
the devices differ significantly from vender to vender
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6.9 VLSI Programmable Logic Devices

Altera MAX 7000 CPLDs
– 16 identical logic array
blocks
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6.9 VLSI Programmable Logic Devices

Xilinx XC4000 FPGA
– Array of configurable
logic blocks (CLBs)
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