Class 15.2 Floataing Point Arithmetic on MIPS.pptx

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Transcript Class 15.2 Floataing Point Arithmetic on MIPS.pptx

Floataing Point Arithmetic on MIPS
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Floating Point Registers
Load, store instructions
Data movement between coprocessors
Load immediate
FP Trap handlers
FP arithmetic instructions
Textbook Ch.4.8 (p.275-301)
Central Connecticut State University, MIPS Tutorial. Chapters 29-32.
Review: MIPS programming model
MIPS contains:
• Integer arithmetic processor
• Floating point arithmetic
processor
• Whole system’s Control
Processor
In this model from the textbook
we can see several additional
groups of MIPS instructions :
• Integer Multiplication
Division instructions.
• Floating point arithmetic
instructions.
• System Control instructions
FP Registers. 32 or 64 ?
 MIPS has 32 single precision
(32 bit) floating point
registers
 The registers are named $f0 –
$f31
 $f0 is not special (it can hold any
bit pattern, not just zero).
 Single precision floating point load,
store, arithmetic, and other
instructions work with these
registers.
Double Precision Registers. The same ?
 MIPS also has hardware for double
precision (64 bit) floating point
operations.
 For this, it uses pairs of single
precision registers to hold
operands.
 There are 16 pairs, named $f0,
$f2, — $f30.
 Only the even numbered register is
specified in a double precision
instruction; the odd numbered
register of the pair is included
automatically.
Both formats of register usage
Single Floating Point Registers
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
=00000000
=00000000
=00000000
=00000000
=00000000
=00000000
=00000000
=00000000
FP8 =00000000
FP9 =00000000
FP10=00000000
FP11=00000000
FP12=00000000
FP13=00000000
FP14=00000000
FP15=00000000
FP16=00000000
FP17=00000000
FP18=00000000
FP19=00000000
FP20=00000000
FP21=00000000
FP22=00000000
FP23=00000000
FP24=00000000
FP25=00000000
FP26=00000000
FP27=00000000
FP28=00000000
FP29=00000000
FP30=00000000
FP31=00000000
Double Floating Point Registers
FP0 =00000000,00000000
FP2 =00000000,00000000
FP4 =00000000,00000000
FP6 =00000000,00000000
FP8 =00000000,00000000
FP10=00000000,00000000
FP12=00000000,00000000
FP14=00000000,00000000
FP16=00000000,00000000
FP18=00000000,00000000
FP20=00000000,00000000
FP22=00000000,00000000
FP24=00000000,00000000
FP26=00000000,00000000
FP28=00000000,00000000
FP30=00000000,00000000
Single precision load instruction
l.s
$fd, addr
• Whatever 32 bits are located at addr are copied into $fd.
• There
is a addr
load delay
slot
• The
address
can be
anafter
ordinary symbolic address, or an
lwc1 instruction.
indexed
address.
• If• the
data
makesaddress
no sense
as abe
floating point value, that is OK for
the
memory
must
this full-word
instruction.
Later on the mistake will be caught when floating
aligned
point operations are attempted
• l.s is pseudo instruction
l.s
a:
$f2,a
.data
.float
[0x00400018]
[0x0040001c]
[0x10010000]
• It is translated into 2 basic
instructions
1.0
0x3c011001
0xc4220000
0x3f800000
lui $1, 4097 [a]
lwc1 $f2, 0($1) [a]
This means load the word to
the Coprocessor 1
Single precision store instruction
s.s
$fd, addr
• Whatever 32 bits are in $fd are copied into addr .
theaddress
memory
address
must
be
• • The
addr
can be
an ordinary
symbolic address,
aligned
orfull-word
an indexed
address.
s.s
$f1,a
• s.s is pseudo instruction
a:
.data
.float
• It is translated into 2 basic
instructions
8.32
[0x00400018] 0x3c011001
[0x0040001c] 0xe4210000
[0x10010000] 0x41051eb8
lui $1, 4097 [a]
swc1 $f1, 0($1) [a]
This means to store the
word from Coprocessor 1
Load, Store Example
## swap.asm
## Exchange the
.text
.globl
main:
l.s
l.s
s.s
s.s
valA:
valB:
.data
.float
.float
values in valA and valB
main
$f0,valA
$f1,valB
$f0,valB
$f1,valA
#
#
#
#
$f0
$f1
$f0
$f1
<-<--->
-->
valA
valB
valB
valA
8.32
-0.6234e4
# 32 bit floating point value
# 32 bit floating point value
# small 'e' only
Data Movement
 Sometimes the floating point
registers are used as temporary
registers for integer data.
 For example, rather than storing a
temporary value to memory, you
can copy it to an unused floating
point register.
 This is OK, as long as you don't try
to do math with them.
 So a complicated calculation with
integers can use float registers for
intermediate results. And a
complicated calculation with floats
can use general purpose registers
the same way.
Data Movement instructions
Instruction
Operation
mov.s fd, fs
copy 32 bits from float register $fs (source) to float register $fd
(destination)
mtc1 rs, fd
move to coprocessor 1
• Copy 32 bits from general register $rs to float register $fd.
• No data conversion is done.
• The source register is $rs and the destination register is $fd, the
reverse of the usual order.
mfc1 rd, fs
move from coprocessor 1
• Copy 32 bits from float register $fs to general register $rd.
• No data conversion is done.
Load Immediate
li.s
$fd,val
load register $fd with val (pseudoinstruction)
li.s
li.s
li.s
$f1, 1.0
$f2, 2.0
$f10, 1.0e-5
# $f1 = constant 1.0
# $f2 = constant 2.0
# $f10 = 0.00001
lui $1, 16256
mtc1 $1, $f1
;li.s
$f1,1.0
# $f1 = constant 1.0
lui $1, 16384
mtc1 $1, $f2
;li.s
$f2,2.0
# $f2 = constant 2.0
lui $1, 14119
;li.s
ori $1, $1, -14932
mtc1 $1, $f10
$f10,1.0e-5 # $f10 = 0.00001
Floating Point Trap Handler Services
Service
Code in $v0
Arguments
Returned Value
print integer
1
$a0 == integer
print float
2
$f12 == float
print double
3
($f12, $f13) == double
print string
4
$a0 == address of string
read integer
5
$v0 <-- integer
read float
6
$f0 <-- float
read double
7
($f0, $f1) <-- double
read string
8
$a0 == buffer address
$a1 == buffer length
allocate memory
9
$a0 == number of bytes $v0 <-- address
exit
10
Single Precision Arithmetic
Instruction
Operation
abs.s fd,fs
$fd = |$fs|
add.s fd,fs,ft
$fd = $fs + $ft
sub.s fd,fs,ft
$fd = $fs - $ft
mul.s fd,fs,ft
$fd = $fs * $ft
div.s fd,fs,ft
$fd = $fs / $ft
neg.s fd,fs
$fd = -$fs
Why we do not need HiLo
in this
case?
 The first instruction computes the absoluteregister
value (makes
a positive
value) of the value in register $fs
 All instructions correspond to one machine instruction.
The result is also floating
 The double precision version of these and many
previously
discussed
point.
So it takes
one 32
instructions has a "d" in place of the "s". bit register.
 So add.s becomes add.d and corresponds to the machine code that
adds double precision.