Transcript Exceptions Another form of control hazard Could be caused by…

Exceptions
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Another form of control hazard
Could be caused by…
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Arithmetic overflow (how do we know?)
Divide by 0
Undefined opcode in instruction
Illegal memory address
Syscall
Handling an exception
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What the system must do:
1. Save address of offending instruction
2. Transfer control to OS at some address that
will handle the exception
3. OS takes appropriate action
4. OS can terminate execution, or continue
using the address saved in 1.
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How this is done depends on processor
implementation (datapath, etc.)
MIPS support for exceptions
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EPC = exception program counter
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contains address of instruction that caused the
exception
Cause = 32-bit register used to record
cause of exception.
mfc0 = instruction to put EPC into one of
general-purpose regs. E.g. mfc0 $s1, $epc
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so that we can return from exception handler
using jr.
Exceptions in pipelined datapath
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Could have exceptions in different stages:
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IF: fetching instruction from memory causes
page fault
ID: illegal opcode
EX: division by 0, overflow
MEM: fetching data causes page fault; illegal
address (protection violation)
WB: no exceptions possible!
Exceptions in pipelined datapath
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Say you execute:
lw $1, 4($3)
add $2, $3, $4
# causes overflow!!!
or $3, $1, $2
bne $1, $3, L
Exception in stage EX
ID
IF
EX
EPC
MEM
WB
Cause
bne $1, $3, L
Instruction
memory
CLK
Register
file
ALU
SE
PC
Overflow detected
0x1240
or $3, $1, $2
Clock:
1
2
3
4
add $2, $3, $4
Data
Memory
lw $1, 4($3)
We need to continue executing lw, but
kill the add, or, and bne instructions –
and start executing the exception
handler instead
Exception in EX – next cycle
ID
IF
EX
EPC
MEM
WB
Cause
exc. instr 1
Instruction
memory
CLK
Register
file
ALU
SE
PC
nop
address of
Interrupt
handling routine
nop
Data
Memory
nop
Clock:
lw $1, 4($3)
Still in pipeline!
1
2
3
4
5
Review and summary 1
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Performance
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CPI: cycles per instruction.
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Execution time = IC * CPI * C
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Where IC = instruction count; C = clock cycle time
Performance: inverse of execution time
MIPS = million instructions per second
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Average CPI based on instruction mixes
Higher is better
Amdahl’s Law:
Exec.time after improvement 
Exec. time affected by improvement
 Exec.time unaffected
Amount of improvement
Review and summary 2
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Differences between single-cycle, multicycle, and pipelined datapaths.
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CPI for single-cycle is 1. Inefficient.
Multicycle: instructions take different # of
cycles to execute. CPI is 3,4, or 5 depending
on instruction type.
Pipeline: fixed CPI = 5 , but best throughput
and performance.
Multicycle: share resources across cycles (e.g.
have one ALU for everything); not so in single
cycle and pipeline (e.g. have at least 3 ALUs).
Functional units
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Many units used the same in all datapaths
(single, multi, pipeline):
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- has address of current instr.
Sign-extend: SE for I-type instructions (e.g.
addi), takes a 16-bit immediate field from
instruction and sign-extends it to 32 bits.
Shift-left-by-2: << 2 - used for adjusting
addresses to be word-aligned.
Branch address calculation:
(sign_ext(imm)) << 2) + (PC+4)
PC
Controls
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Basic controls for some functional units:
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Register file
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Memory
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MemRead – want to read data
MemWrite – want to write data (must be off by default!)
ALU
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Write enable: only 1 when writing a register
Operation to be performed
PC
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PCWrite – set to 1 when want to write PC. Only exists in
multicycle datapath. We write PC on every cycle in
pipelined/single cycle versions!
Controls continued
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Decisions to be made in the datapath (i.e. mux
controls):
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ALUSrcA, ALUSrcB: choose ALU inputs from:
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register (read from register file)
Immediate (sign-extended, zero-extended, etc.)
Forwarded data (in pipelined design)
PCSource: select between PC+4, branch address, and
jump address
RegDst: select between rd and rt for destination
register
MemtoReg: in pipeline, select between memory output
and ALU output to write back to register file.
IorD: in multicycle, select whether we use memory to
read instruction or data.
Pipelining
instr1
instr2
Instructions
instr3
instr4
Clock
Cycle 1
Clock
Cycle 2
IM
Reg
IM
Clock
Cycle 3
Clock
Cycle 4
Clock
Cycle 5
Clock
Cycle 6
Clock
Cycle 7
DM
Reg
IM
DM
Reg
IM
DM
Reg
DM
Time
Pipeline hazards
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Data hazards
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Structural hazards
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Instruction dependent on another instruction still in
pipeline.
E.g.: add $1, $2 $3; or $3, $1, $1
Resolve by forwarding and/or stalling
where two instructions at different stages want to use
the same resource.
Resolve by adding more hardware
Control hazards
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Branches, interrupts, exceptions
Wrong instruction in pipeline following branch,
because branch address/condition not ready in time
Fixes: stall, redesign pipeline, specify delay slots,
branch prediction