Transcript Document 7922920

University of Houston
Networking 102
Dr Fred Zellner
[email protected]
Clocking
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Clocking in the Digital Network
•
Stratum Levels
•
Clocking Distribution
— Single Point versus Multiple Points
•
Timing Differences
•
Correcting Timing Errors
— Buffers
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Clocking
The most important aspect in digital networking is
clocking. The clock that quantifies the analog signal
must be the same clock that reconstructs the signal at
the other end. The only way to assure that the clock is
accurate within the entire digital network is to have
only one clock.
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Clocking
This is the way the first digital network was
designed and setup in America. AT&T set up a
atomic clock which sent its time signals to each of
the switching offices by means of the internal data
network.
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Clocking
The different levels of clocking accuracy are
called Stratum levels. This source of clock was
called Stratum-1. Telephone companies distribute
the analog clock frequency to the first working
level which was called Stratum-2. This clock
source is still very accurate but is starting to
show signs of a measurable difference.
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Clocking
• 1) Clock Recovery
• 2) Isochronous Clocking
• 3) Ones Density
• 4) The Phase Locked Loop (PLL)
• 5) Digital Data Services or 56 Kbps Data
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Clocking
Getting from a Stratum Level-2 to a Level-3
telephone company office is achieved primarily over
the digital network. The accuracy of a Stratum Level3 clock relies on averaging time from a number of
incoming digital lines, which results in a new nodal
clock. Telephone company offices with Digital CrossConnect Systems (DCCS) and DDS Hub offices use
this Stratum level-3 nodal clock. It is the highest level
of timing accuracy accessible to end-user facilities.
.
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Clocking
This now brings us down to the clock internal to the
end-user’s terminal. Since the terminal relies on phase
locking (PLL) this frequency from an internal crystal ,
the results are going to be less accurate than the clock
coming to your location. In order to connect to the
public network, you must have “receive timing on
transmit”. This means you must use the clock coming
in and the clock generator for the signal going out.
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Clocking Distribution
Master Clock
Regional Message Switch
Digital Cross-Connect
Network Timing Source
Toll Office Switch
End Office Switch
Digital Office Timing
Digital Channel Bank
End User Terminal Equipment - Customer Owned Switch
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Clocking Distribution
Telephone Company Distribution
How many level-1 clocks exist in a particular telephone
company network depends on their basic needs. TransCanada Telephone selected two master clocks--One at
Ottawa and the other in Calgary. AT&T had one master
Clock at Hillsboro.
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Clocking Distribution
Telephone Company Distribution
Other United States telephone companies have
opted for independence from AT&T’s Reference
frequency and have installed their own master
clocks. Both Sprint and MCI have their own
clocking schemes and employ multiple high level
clock sources.
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Telephone Company
Distribution
Many private companies have their own clock to time
their networks because multiple carriers used or the
number of different types of equipment at the customer
site. As more Stratum Level-1 sources spring up across
the country, look for a slight increase in bit slips
between networks.
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Clocking Distribution
Satellite
Telephone companies and some other operators of Large
area networks use timing sources based on Stratum-1
clock sources located in satellites. Time can be broadcast
to all of the network office facilities at the same time,
there-by assuring the same clock time at all locations.
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Typical Clocking Distribution
Clock 1
Clock 3
Clock 2
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Clocking Differences
Integrated digital networks are timing clock oriented.
Clocks open and close logic gates to expected data
pulses. When two clock sources appear in the same
network, confusion abounds and errors ensue. Staying
within one network only lessons the problems
encountered. Your main concern is to reduce timing
difference to a minimum, and thereby limit the number
of bit slips in the network.
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Clocking Differences
There are several ways to reduce the clock
differences. One method is adequate buffering
between equipment and facilities. Another is slavetiming analog portions of your network to the main
clock source.
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Clocking Differences
BIT SLIPS
If you have two clocks in the same network, the
difference between them will eventually result in a bit
slip. A bit-slip results from one one clock source being
faster or slower than the other. How often a bit-slip
occurs depends on the timing difference. Digitized
voice circuits go unscathed from even very high rates
of bit-slips.
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Clocking Differences
Analog data circuits without built-in error correction may
experience an error. Never the less, digital data circuits
feel even the lowest number of bit-slips. Bit-slip can be
either an extra bit inserted in the data stream or the
omission of an expected bit.
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Clocking Differences
BIT STUFFING
Reducing the clock difference between telephone
company offices is a controlled timing difference.
Telephone multiplexes purposely adds bits into the
composite stream to adjust for the differences. Bit
stuffing is a better name for this process. Stuff bits
always appear in the aggregate data stream. If the
transmitting end senses a need for a stuff bit, it
notifies the other end to use one of the bits.
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Clocking Distribution - Error Correction
If data comes in too
slow the buffer runs
runs low and the
pointer will reset
at the middle.
Data comes in either too
fast or too slow.
If data comes in
too fast the buffer
overflows & the
pointer will reset at
the middle
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Clocking Differences
BUFFERING
Buffering provides a way to reduce the number of slips
between two clock sources. It doesn’t eliminate slips, but
instead delays when they will happen. The buffer, after a
bit slip goes back to the staring position. When the read
clock is faster than the write clock, there comes a time
when the buffer doesn’t have any space in it or any bits
to give. This results in a bit gap in the data output. Bit
gaps also become bit slips.
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Clocking Differences
BUFFERING
If the Write Clock is faster than the Read clock the buffer
will fill up, resulting in the buffer emptying, causing a
bit slip. Buffers have a major drawback adding delay to
the network. Increasing the buffer’s size to extend the
interval between bit slips, increasing the delay within the
system.
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Clocking Differences
COMPOSITE FREQUENCY SUPPLIES
Network offices have primary frequency generators that
phase lock to an in coming master frequency source.
The primary operating frequency in any telephone
network is 4kHz. Multiples of 4kHz run anything from
the individual channel to the very highest facility carrier
system. A composite clock supply furnishes both 8kHz
and 64kHz. Timing the Digital Signal Equipment (1
digital voice call) needs both the 8kHz and the 64Kbps
clock
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Clocking Differences
CLOCK RECOVERY
At each point in the network the clock is recovered by
a Phase Locked Loop circuit. Every device that has a
connection to the network must conform to loop timing
on Transmit. What this means is that every data stream
coming into a customer interface must trigger a PLL
circuit. This clock generated by this PPL will loop the
input clock back to the transmit side of the interface.
This is done to make sure the timing accuracy level of
the clock coming into the customer equipment is the
same clock that will go back into the network facility.
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Network Clocking
Network Clocking
Repeater
Repeater
Repeater
Repeater
T1 Multiplexer
T1 Multiplexer
CPE Equipment
CPE Equipment
CPE Equipment
Regenerator
Phase-Locked Loop
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Clocking
ISOCHRONOUS
Isochronous clocking is the type of clocking used in the
digital telephony network. The PLL produces a constant
clock signal signal using the incoming bits as triggers to
maintain the accuracy of the circuit. You can view this
circuit as kind of a flywheel. Once the flywheel gets up
to speed it will maintain the same RPM with only a
small amount of energy to keep it at the same speed.
The energy used in the PLL is the incoming pulse.
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Clocking
ISOCHRONOUS
If the incoming signal comes in before the circuit
expects it the PLL speeds up a little as to adjust the
clock output. The opposite occurs when the signal
comes in after it is expected. It is necessary to make
sure the network has a certain ones density to keep all of
the PLL circuits in the network connection at the
optimum timing accuracy.
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Thank You !
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