Transcript ECE-L304 Lecture 5

ECE-L304 Lecture 5
Step 3 Lab
LED
Array
Complete
Resistor
Array
Self-Clocked
ADC
DAC
8-pin header
Data Bus Test Port
Timing & Filter
Components
External Components
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Step 4

Purpose

Introduce the static RAM chip


Write mode, read mode
Introduce the address generator

Step the address from 00H to FFH (256 steps)
using 8 bits


“H” indicates hexadecimal format
Introduce control

Record 256 words in RAM, then play back
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This Week
 Step 4 Prelab
 Skim the data sheet for the 1 MB RAM chip
 Look for control and timing information
 Step 4 Lab


Simulate a simple data acquisition system
with memory
Answer a few short questions
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Static RAM
An Introduction

Static RAM is read/write storage that is
volatile


Volatile - when power is removed, contents are
lost
Words are written to or read from sites
determined by the address location under
RE/WE (read enable/write enable) control


An 8k x 8 RAM has a 13-bit address bus giving 213
= 8192 8-bit locations, or 64kB (65,536)
A 128k x 8 RAM has a 17-bit address bus, giving
217 = 131,072 8-bit locations, or 1MB
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Static RAM
Read and Write Timing

Write Operation

A[12-0]
stable
D[7-0]
stable
RE
WE
ECE-L304 Lecture 5
After the
address and
data have been
stable for a
setup time,
pulse the write
enable
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Static RAM
Read and Write Timing

Read Operation

A[12-0]
stable
WE
RE
D[7-0]

valid
ECE-L304 Lecture 5
Once the
address is
stable, raise the
read enable
After a settling
time, the data is
valid
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What will you do?

Part 1

Write two data bytes to two RAM locations
and read them back



Learn to display data in hex format in Probe
Observe Read/Write operations and timing
Part 2

Write 8-bit ADC data to 256 locations and
read it back
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Data Acquisition System
Operation

Repeat n times to store:




Repeat n times to retrieve:
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


Sample an analog signal
Convert to digital
Write to the next RAM location
Read from next RAM location
Convert to analog
Display analog signal
n = number of RAM locations
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Address Generation
DAC
RAM
ADC
Control
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Step 4 - Part 1
DSTM1
S16
RAM8kX8break
A[16-0]
0s 0005
1us 0006
2us 0005
3us 0006
FORMAT=4444
FORMAT=1111
0s 0000
0.25us 0010
0.75us 0000
1.25us 0010
1.75us 0000
2.00us 0001
RW[3-0]
S4
DSTM2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RW0
RW1
RE
WE
R[7-0]
R7
R6
R5
R4
R3
R2
R1
R0
R7
R6
R5
R4
R3
R2
R1
R0
W7
W6
W5
W4
W3
W2
W1
W0
W7
W6
W5
W4
W3
W2
W1
W0
ECE-L304 Lecture 5
FORMAT=44
0s 54
1us 36
2us XX
W[7-0]
S8
DSTM3
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Step 4 - Part 1

Simulate the following activities

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

Write data 54H from port W to address 5H
Write data 36H from port W to address 6H
Read the contents of address 5H to port R
Read the contents of address 6H to port R
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Step 4 - Part 2
DAC8break
U10
V
AOUT
3
4
1k
R1
DB7
DB6
DB5
OUT DB4
DB3
DB2
REF DB1
DB0
AGND
13
12
11
10
9
8
7
6
RCO_
RAM8Kx8break
V
U5
16
17
18
19
20
21
22
23
5
0
0
V
AIN
1
2
V2
3
4
0
FREQ = 1kHz
VAMPL = 5V
V
ADC8break
U11
R3
1k
0
5
R2
1k
0
IN
DB7
DB6
CNVRT
DB5
DB4
STATDB3
DB2
OVERDB1
DB0
REF AGND
16
15
14
13
12
11
10
9
V
R[7-0]
R7
R6
R5
R4
R3
R2
R1
R0
V
W7
W6
W5
W4
W3
W2
W1
W0
W[7-0]
24
25
26
27
28
29
30
31
R7
R6
R5
R4
R3
R2
R1
R0
W7
W6
W5
W4
W3
W2
W1
W0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RE
WE
A[7-0]
9
15
1
2
3
4
5
6
7
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
VOFF = 5V
RCO G
QA RCK
QB
CCKEN
QC CCK
QD CCLR
QE
QF
QG
QH
14
13
12
11
10
U8A
LO
DSTM1
U12A
2
3
2
3
1
1
HI
74LS08
74LS08
74LS590
LO
V
14
15
CLK
U9
74LS107A
U6A
RE
U7A
WE
2
3
3
1
V
74LS08
8
V1
OPPVAL = 1
STARTVAL = 0
DELAY = 0
ONTIME = 31.25us
OFFTIME = 31.25us
2
1
J
Q
CLK
Q
R K
L
C
3
1
HI
12
4
HI
HI
0
256Vdc
0
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Step 4 - Part 2

Why are the two AND gates (U8A,
U12A) needed?

The address must be set up and stable
before the WRITE signal is applied
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Step 4 - Part 2
RE
WE
RCO_
{A[7:0]}
{R[7:0]}
{W[7:0]}
Z
10V
5V
0V
0s
V(AIN)
4ms
V(AOUT)
8ms
12ms
16ms
20ms
24ms
28ms
32ms
Time
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Step 4 - Part 2
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Step 4 - Part 2

Simulate the following activities



Write 8-bit ADC data to the lowest 256
addresses in memory
Read the lowest 256 addresses to the R
port
Generate an analog signal using these 8bit words
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The 8-Bit Counter



The 74LS590 binary counter
Used to generate addresses
Ripple Carry Out pin makes it easy to
set up multiple-chip counters
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The 8-Bit Counter
Multiple Chips
LO
CLK
HI
G
LO
G
CCLK
CCLK
CCLKEN RCO
A7
RCLK
CCLKEN RCO
A7
RCLK
CCLR
A7
A6
A6
A5
A15
A6
A14
A5
A5
A13
A4
A4
A4
A12
A3
A3
A3
A11
A2
A2
A2
A10
A1
A1
A1
A9
A0
A0
A0
A8
HI
ECE-L304 Lecture 5
CCLR
20
RAM Control
RCO
CLK
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Your Hardware
Static RAM

NEC uPD431000A 128k x 8 Static RAM


RAM - Random Access Memory
128k x 8 - storage for 131,072 8-bit words


Data is transferred in and out in parallel
8-bit tristate data bus



Input, output, high impedance
Status controlled by CE1, CE2, WE, OE pins
Control truth table on datasheet
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Your Hardware
Static RAM

Address locations




The 128k x 8 RAM has a 17-bit address bus (217 =
131,072)
You will use the 16 address bits (216 = 65,536)
generated by two 74LS590 chips and design a
simple circuit to provide the 17th address bit
This gives a total memory of 1024k
You have the option of using 16 bits for less than
full credit
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Step 4 Deliverables

Complete Part 1 Simulation


Part 1 Schematic
Part 1 Simulation


Are proper read/write timing rules followed?


Plot A[15-0], W[7-0], RW1, RW0, R[7-0] vs time over
span of 0 to 4 us
Relationships between address, data, RE, WE
Is the data read from memory identical to
what was written?
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Step 4 Deliverables

Complete Part 2 Simulation


Part 2 Schematic
Part 2 Simulation


Are proper read/write timing rules followed?
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Plot W[7-0], R[7-0], WE, RE, RCO_, AIN, AOUT vs time over
one complete read/write cycle
Relationships between address, data, RE, WE
Does the data read from memory and converted to
analog (AOUT) match the input waveform (AIN) to
the resolution of the system?
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Step 4 Deliverables


How would you correct the timing flaw at the
transition from write to read? Repeat the
simulation with the correction and include the
results in your report.
Why is there a lag time in the READ
operation between the time RE goes high and
when the data is valid?
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