EMU Muon Port Card Project M.Matveev

Rice University March 20, 2002

MPC Functions

• One board per CSC Sector (8 or 9 chambers), • Resides in the middle of the peripheral VME 9U crate.

• Receives up to 2 muons from each of 8 or 9 Trigger Motherboards every 25 ns • Selects 3 best muons out of 18 possible • Transmits these 3 muons in ranked order to Sector Processors residing in the counting room over three 100 m optical cables every 25 ns

MPC Block Diagram

UCLA MEZZANINE CARD (XCV600E) OPTO 3 OPTICAL CABLES TO SECTOR PROCESSOR OPTO FINISAR FTRJ-8519-1-2.5

OPTICAL TRANSCEIVERS TLK2501 SERIALIZERS OPTO 9U x 400 MM BOARD SER SER SER CCB INTERFACE SORTING LOGIC INPUT AND OUTPUT FIFO FPGA VME J1 CONNECTOR VME INTERFACE CCB CCB TMB_1 TMB_2 TMB_3 TMB_4 TMB_5 TMB_6 TMB_7 TMB_8 TMB_9 CUSTOM PERIPHERAL BACKPLANE SN74GTLP18612 GTLP TRANSCEIVERS

Sorter FPGA

TMB 1 DFF VME FIFO A DFF VME FIFO A MUX MUX TMB 2

•• •

TMB 9 VME CCB CCB INTERFACE SORTER “3 OUT OF 18” 9 4 PIPELINE MUON 1 4 PIPELINE MUON 2 54 MUX DFF MUON 1 FIFO_B MUON 1 VME DFF MUON 2 FIFO_B MUON 2 VME DFF MUON 3 FIFO_B MUON 3 VME WINNER

FPGA Requirements

• 9 input links from Trigger Motherboards, 32-bit @ 80 MHz per link (288 inputs total) • 3 output links to data serializers, 16-bit @ 80 MHz per link (48 outputs total) • 1 output status link (winners) 9-bit @ 80 MHz to TMBs • Input and output FIFO buffers for testing purposes • Interfaces to VME and Clock and Control Board (CCB) (~75 inputs and outputs total for both) • FPGA should have ~470 bandwidth input/output pins and ~28 Gbps total

TMB - to - MPC Frame Format

15 Vpf 14 13 12 Quality[3..0] 11 10 9 Frame 1 8 7 CLCT Pattern ID[3..0] Frame 2 6 5 4 3 2 Wire Group ID[6..0] 1 0 15 1 14 0 13 0 12 0 11 10 9 Bx1 Bx0 ER 8 L/R 7 6 5 4 3 Half-Strip ID[7..0] 2 1

CLCT Half-Strip Pattern ID is between 0 and 159 CLCT Pattern encodes the number of layers and whether the pattern consists of half-strip or di- strips L/R – Bend Angle Bit indicates whether the track is heading towards lower or higher strip number Wire Group ID is between 0 and 111 and indicates the position of the pattern within the chamber VPF – Valid Pattern Flag indicates a valid LCT that has been found by TMB and being sent in the current clock cycle ER – Synchronization Error bit BX[1..0] - The less significant bits of Bunch Crossing Counter

0

MPC – to – SP Frame Format

15 Vpf 14 13 12 Quality[3..0] 11 10 9 Frame 1 8 7 CLCT Pattern ID[3..0] Frame 2 6 5 4 3 2 Wire Group ID[6..0] 1 0 15 14 13 CSC_ID[3..0] 12 11 10 9 Bx1 Bx0 ER 8 L/R 7 6 5 4 3 Half-Strip ID[7..0] 2 1

CLCT Half-Strip Pattern ID is between 0 and 159 CLCT Pattern encodes the number of layers and whether the pattern consists of half-strip or di- strips L/R – Bend Angle Bit indicates whether the track is heading towards lower or higher strip number Wire Group ID is between 0 and 111 and indicates the position of the pattern within the chamber VPF – Valid Pattern Flag indicates a valid LCT that has been found by TMB and being sent in the current clock cycle ER – Synchronization Error bit BX[1..0] - The less significant bits of Bunch Crossing Counter

0

CSC Numbering scheme • In the present design the CSC_ID=1 corresponds to TMB1 on the peripheral backplane, CSC_ID=2 corresponds to TMB2 and so on T M B D M B T M B D M B T M B D M B T M B D M B T M B D M B M P C C C B T M B D M B T M B D M B T M B D M B T M B D M B 1 2 3 4 5 6 7 8 9

Preliminary results of FPGA Design • Targeted to Xilinx XCV600E-7FG680 FPGA (UCLA mezzanine card) • 461/512 input/output pins used (89%) • 5009/6912 slices used (72%) • 42/72 BlockRAMs used (58%) • 44.13 Mhz maximum performance (FPGA Express synthesis) Latency • 100.0 ns (4.0 BX) total FPGA latency including: - 1.0 BX input latching @ 80MHz and multiplexing with FIFO - 1.5 BX sorting “3 out of 18” - 0.5 BX data merging - 0.5 BX output multiplexing and latching @80MHz - 0.5 BX data latching into TLK2501 serializers • 24 ns serialization delay (TLK2501 transmitter @ 80 MHz)

MPC Board Design Status • GTLP Backplane Interface to 9 TMB’s (completely defined) • Mezzanine Card pin assignment done • A24D16 VME Interface based on glue logic (address latches, data buffers, comparators, DS/DTACK logic, CSR0) • CCB Interface is completely defined • Optical Data Format to SP has been agreed • Preliminary FPGA design is done (XCV600E-7FG680) • MPC draft specification is prepared • Schematic design ~80% completed • 6 free FPGA were obtained (Xilinx donation) • Mezzanine cards are ordered through UCLA

CCB for Track Finder Crate

• Same CCB for peripheral and Track Finder crates • 20 sets (main 9U board + Altera-based mezzanine card) have been fabricated so far • 15 boards are assembled and tested • 2 boards will be used for Track Finder tests (UF & Rice)

TTCrx Clock40Des1 Jitter

Mezzanine Card TTCrx ASIC operating voltage Clock40Des1 jitter, ps (no BC, no L1A) Clock40Des1 jitter, ps (BC commands + L1A) ECP680-1102-630C +5.0V

153 183 +3.3V

170 215 ECP 680 1102-610B +5.0V

330 360 New TTCrx Old TTCrx

Optical Test with TTCrx

PC B I T 3 T T C V I

• ••

T T C V X

• • ••

VME 9U 100 m COPPER CABLE C C B

•

TTCrx

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1 m OPTICAL CABLE 40 Mhz O P T O

• •

Clock multiplier 100 m

• •

O P T O ERROR VME 6U • OLD AND NEW TTCrx BOARDS WERE TESTED WITH 40.00 Mhz CLOCK SOURCE FROM TTCvx MODULE • 40.00 Mhz CLOCK WAS MULTIPLIED BY 2 BY AV9170 CHIP • NO ERRORS OBSERVED IN PRBS TEST FROM ONE OPTOBOARD TO ANOTHER AT 80.00 Mhz (BER < 10 -13 c -1 )

TTCrx Clock40Des1 Jitter

Conclusion • Jitter is lower for the newest TTCrx ASIC (Version 3.1, 12/2001) • Jitter increases if the broadcast commands and L1A are transmitted from TTCvi/TTCvx • Jitter distribution for ASIC Ver.3.1 is close to gaussian. Jitter distribution for old ASIC looks differently • Jitter is lower if the new ASIC is powered from +5V • Jitter introduced by any of two TTCrx ASICs and other components in the clock distribution circuitry at our testing setup is tolerable for TLK2501 transceivers operating at 80.00 Mhz