Transcript FPGA FREQUENCY DOMAIN BASED GPS COARSE ACQUSITION PROCESSOR USING FFT

FPGA FREQUENCY DOMAIN BASED GPS COARSE ACQUSITION PROCESSOR USING FFT
Cyprian Sajabi and Chien-In Henry Chen, Department of Electrical Engineering, Wright State University Dayton, OHIO, 45435
David M. Lin and James B. Y. Tsui RF Technology Division, Sensors Directorate, Air Force Research Lab, Wright Patterson AFB, OH 45433
ABSTRACT
•
In this paper we describe the use of the FFT on an FPGA to perform lock
on coarse acquisition (C/A) code and carrier frequency in a global
positioning system (GPS) receiver. A novel technique of sub-sampling is
used in this system to obtain data block sizes that match hardware
limitations. The system uses 10 ms of data to perform the lock with 6 ms
of processing time and theoretically can operate on signals 20 db below
the noise floor.
y(n) 5 MHz
•
C/A codes may be out of synch. Need to
synchronize local C/A code with received C/A
code. C/A phase unknown.
•
cacode
module
8 bits,
50000 samples
DDS
Buffer
y(n) 100 MHz
c_e(n)
7 bits real
100 MHz
d_c(n), complex
14 bits, 40960 samples
A 2-D search of C/A code phase (up to 1,023
chips) and Doppler shifts (+/- 5 KHz) – very
time-consuming in time-domain.
PROBLEM STATEMENT
• GPS coarse/acquisition (C/A) code receiver receives weak
signals(15 dB below noise). 1ms of data is generally used and
this is sampled at 5 MHz due to limitations of software
processing. Acquisition is done in the frequency domain.
• Weaker and or longer(>1ms) signals require greater
processing. P and M code signals require more than 1ms of
data.
• Data acquisition and digitization at a higher speed(>5MHz)
require hardware FFT such as on an FPGA, a flexible
prototyping platform
c_a(n), 16 bits,
100 MHz, real
row#
4096
FFT
Subsample
Discard conjugates
4096 FFT
D_C(F) complex ,6 bits
Circular Correlation can find Code phase
D_S_P(F)
D_C(F)*
d_s(n) , 11 bits
Collected
data
Acquisition
Beginning of
C/A code
Despread
Spectrum
Continuous
wave signal
Find
carrier
frequency
Tracking
program
d_s(n)
code phase
13 bits
Fifo_0
d_s(n)
•
Fifo_9
10 POINT DFT/SORTING DOMAIN
d_s(n)
C/A CODE
Read and
write
Address
generation
Continuous wave signal
FREQUENCY-DOMAIN APPROACH
Circular correlation
of
x(n)
and
h(n):
N 1
a ( n) 
d_s(n)
DDS for
I and Q
channels
C/A code
Generator
Control
Read and
write
Address
generation
m 0
• Perform the equivalent of circular correlation in the
frequency domain as follows:
• Take FFT of local C/A code and baseband input signal.
Call them C_A(F) and D_C(F) respectively.
• Take complex conjugate of D_C(F), call it D_C(F)*.
• Point-multiply D_C(F)* and C_A(F), call this result
D_S(F).
• Take IFFT of this D_S(F), call it d_s(n). This is the
circular correlation result.
• The location of the peak value of d_s(n) can be used to
infer C/A code phase.
•
•
Data
Key:
•
•
10-pt FFT operation on data from FFT_2048 domain
•
Sorting of FFT_10 results.
•
Calculation of Code Phase and Doppler shift
RESULTS AND CONCLUSION
•
Write and Read Address
generation
Component
(counter_2048)
25
4096
FFT
C_A(F)
or
D_C(F)
2048 FIFO
cplx mult_1
C_A(F)
1-2
Demux
(cplx)
2048
RAM
SYNTHESIS RESULTS
C_A(F)
D_S(F)
D_C(F)
CORRELATION SUM
10
next stage control
0.4
5
SPREAD SIGNAL
W ITH CARRIER
-0.6
Key:
0
0
500
-0.8
1000
1500
RELATIVE SHIFT OF h(n) and x(n)
-1
0
200
400
600
800
1000
MULT
18X18
36
4
3
0
5,264
1,009
10,129
0
112
Dual port RAM 0
27
0
0
49
0
Dual Port RAM 1
21
0
0
96
0
4,096 FFT
5,227
7,703
6,977
39
27
2,048 IFFT
4,477
7,736
6,286
17
40
43
57
61
0
0
10 point DFT
Control
Data
Address
•
Design performs lock in 6 ms at 100 MHz.
•
Design can theoretically lock onto signals with -20
dB SNR with a frequency resolution of 100 Hz.
•
Requires approximately 16,000 logic slices and 200
multipliers, allowing it to fit on medium sized FPGA.
-0.2
-0.4
Block RAMs
CONCLUSION
Synchronization and
previous
stage control Control
0.6
0
Slice FF’s 4-input LUTs
15
0.8
0.2
Slice
#
51
DDS
1
Xilinx Virtex-II Pro FPGA was targeted. Features
include 196 built-in 18X18 multipliers, Dual port
RAMs and Digital clock management.
FFT_4096 DOMAIN
c_a(n)
or
d_c(n)
Data
Control
Address
Captures 50,000 point frames (10 ms) at 5 MHz.
Streams out 4,096 point blocks at 100 MHz to
FFT_4096.
Basebands and “subsamples” data at 100 MHz.
Regulates the generation and storage of the C/A
code.
DDS freq: (1.25 MHz – 4 KHz) to (1.25 MHz + 5 KHz).
•
•
Synchronization
and Control
previous
stage
control
next stage control
 x ( m) h ( n  m )
D_S_P(F)
c_a(n)
Synchronization and
Control
Key:
Final
Calculation
circuitry
c_a(n)
or
d_c(n)
20
SPREAD SIGNAL
parallel to
serial bubble
sorting
module
max_ find_0
Data valid
NAVIGATION DATA
c_e(n)
Dual Port
RAM 1
(complex)
Max_find_2
Max find_1
Doppler shift
PN PERIOD
DATA PERIOD
2-1
Multiplexer
(complex)
d_c(n)
D_S_P_MAX_1(F)
D_S_P_MAX_0(F)
D_S_P(F)
Code phase
• Navigation data is multiplied or “spread” by the
coarse acquisition (C/A) code, which is a
pseudorandom noise (PN) binary sequence generated
by a Linear Feedback Shift Register (LFSR).
• The C/A code belongs to a family of PN sequences
known as Gold Codes designed for security.
• The Gold Code sequence is 1,023 bits or “chips” long.
• The navigation data bandwidth is 50 Hz, while the C/A
code bandwidth is 2.026 MHz. The
• The Signal is then mixed up to RF for transmission
from GPS satellite to receiver.
• Transmitted signal has 2.026 MHz Bandwidth.
• Spread spectrum transmission uses increased
bandwidth, but provides more secure communication
and Code Division Multiple Access (CDMA).
Dual Port
RAM 0
y(n)
c_a(n)
or
d_c(n)
are complex
Indices
cplx mult
* FIFO data
Data
Performs storage and parallel processing of frames
from 2,048 IFFT.
DATA CAPTURE DOMAIN
y(n)
(FIFO empty signal)
Control
10
point
DFT
C/A code
Next stage control
read enable
to all FIFOs
Key:
C/A coded input signal
GPS/SPREAD SPECTRUM BASICS
d_s(n)
next stage control
DATAFLOW PARTITIONED INTO FOUR FUNCTIONAL
DOMAINS:
– Data Capture Domain( 5 and 100 MHz clocks)
– 4,096 FFT domain (100 MHz clock)
– 2,048 IFFT domain (100 MHz clock)
– 10 point DFT/Sorting Domain(100 MHz clock)
Carrier
frequency
2048 FIFO_9
Synchronization
and Control
11 bits
1:10
Demux
11 bits
d_s(n)
previous
stage control
carrier
frequency
10 PT DFT
D_S(F) conj, 11 bits
2048 IFFT
Decode the
row, stack
and column
data
* d_s(n)
16 bits
D_C(F)* 6 bits
discard conjugates
col# 11 bits
D_S_P_MAX(F)
23 bits
2048 FIFO_0
1-10
Demux
(cplx
data
and
write
enable
signal)
stack# 4 bits
find max of
each frame
of 10
C_A(F)
conj 9 bits
2048
IFFT
D_S(F)
D_S_P_MAX(F)
23 bits
col#
row#
9 bits
d_s(n)
d_s(n)
row# 4 bits
find max of
each batch
of 2048
C_A(F)
complex
-1 * imaginary part
•
find max of
each stack
of 10
Subsample
7 bits
complex
Doppler shift unknown, must be found.
•
FFT_2048 DOMAIN
OVERALL ARCHITECTURE OF
GPS C/A PROCESSOR
ACQUISITION AND DEMODULATION
OF SPREAD SPECTRUM SIGNALS
1200
•
The above C/A code shift is around 604 samples.
2000
2500
•
Regulates storage of C_A(F)
•
Synchronization of C_A(F) with D_C(F) for multiplier
•
Synchronizes start IFFT_2048 with start of D_S(F).