Transcript 5. Combinational Circuits Objectives types of combinational circuits

CSI-2111 Structure of Computers I
page 5-1
5. Combinational Circuits
 Objectives:
To recognize the principal
types of combinational circuits
 Adders




and subtracters
Decoders, comparators, converters
Multiplexers and demultiplexers
Logical programmable: ROM, PAL, PLA
Arithmetic logic unit (ALU)
 Various
combinations for their analysis
and synthesis, and the synthesis of
functions in general.
CSI-2111 Structure of Computers I
page 5-2
5.1 Adders and Subtracters
Already discussed the adder (Chap. 2)
 Subtracters

– Half-subtracters, elementary
I
D
B
A
E
– Adders/subtracters
– Subtracters with several bits
CSI-2111 Structure of Computers I
page 5-3
5.2 Decoders
 Decode
 It
A
0
0
1
1
B
0
1
0
1
a binary word.
has n inputs and m  2n outputs.
D0
1
0
0
0
D1
0
1
0
0
D2
0
0
1
0
D3
0
0
0
1
A
B
21
20
Decoder
2 to 4
0
D0
1
D1
2
D2
3
D3
CSI-2111 Structure of Computers I
Synthesis with decoders
 Any
binary function f(x1, x2, ..., xn) can
be realized simply by a n x 2n decoder
and an OR gate.
– Example: Elementary adder
Decoder with Enable (E) input
– E allows enable/disable a decoder.
– If E = 0, all the outputs are to 0.
– Useful in the synthesis of large decoders
page 5-4
CSI-2111 Structure of Computers I
page 5-5
Synthesis with decoders *
 Elementary
adder
S (X, Y, Z) = Sm (1, 2, 4, 7)
C (X, Y, Z) = Sm (3, 5, 6, 7)
X
Y
Z
0
1
22
2
3
21
3x8 4
20 decoder 5
6
7
S
C
CSI-2111 Structure of Computers I
page 5-6
Synthesis of large decoders
4
x 16 decoder using two 3 x 8 decoders
x
y
z
22
21 3 x 8
decoder
20
E
8
x
y
z
22
21
8
D0 to D7
w
20
3x8
decoder
E
D8 to D15
CSI-2111 Structure of Computers I
page 5-7
Synthesis of large decoders *
4
x 16 decoder using 2 x 4 decoders
w
x
0
21 2 x 4 1
20 decoder 2
3
E
y
z
21
4
y
z
21
4
y
z
21
4
y
z
21
4
2x4
0
2 decoder
E
2x4
20decoder
E
2x4
20decoder
E
2x4
0
2 decoder
E
D0 to D3
D4 to D7
D8 to D11
D12 to D15
CSI-2111 Structure of Computers I
page 5-8
5.3 Magnitude Comparators
 Carry
out the comparison of two binary
numbers.
– The comparator of binary numbers (A and
B) of four bits to indicate if A>B, A<B or
A=B. It has moreover three entries (A>B,
A<B and A=B) allowing the sequence of the
circuits to compare numbers of more than
four bits (in cascade).
CSI-2111 Structure of Computers I
page 5-9
5.4 Code Converter
 Achieves
the conversion of information
in one form of binary representation to
another form of binary representation.
– Examples:
 1CF
to 2CF
 BCD to Excess-3
 BCD to representation in 7 segments
– As in a display
– Various options (0 to 9, 0 to 9 with values indifferent
for entries 10 to 15, 0 with F, etc.)
CSI-2111 Structure of Computers I
page 5-10
5.5 Multiplexers
 Use
Multiplexing
Demultiplexing
Source 0
Destination 0
Source 1
Destination 1
Source 2n-1
.
.
.
Un seul lien
Multiplex
.
.
.
Demultiplexer
Destination 2n-1
CSI-2111 Structure of Computers I
page 5-11
Multiplexers
– Multiplexer (MUX) selects one out of 2n
inputs of information and directs it to the
output.
– Example: 4-to-1 Multiplexer.
S1
0
0
1
1
S0
0
1
0
1
Y
D0
D1
D2
D3
D0
0
D1
1
D2
2
D3
3
MUX
4-to-1
S
21
20
S1
S0
Y
CSI-2111 Structure of Computers I
Synthesis with multiplexer
 That
is to say a binary function f(x1,
x2…, xn), its realization with a
multiplexer is done according to the
following procedure:
1. Develop the Truth Table of f.
2. If the multiplexer is rather large
(2n to 1 MUX)
 Then
not of problem. All is direct!
 If not… use 2n-1 to 1 MUX.
page 5-12
CSI-2111 Structure of Computers I
page 5-13
Synthesis with too small MUX
 Example:
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
= m (2, 3, 5, 6)
f(A,B,C)
A
0
0
1
1
f
C
{
B
0
1
0
1
f
4-to-1
MUX
A
B
f
CSI-2111 Structure of Computers I
page 5-14
Synthesis with too small MUX *
 Example:
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
= m (2, 3, 5, 6)
f(A,B,C)
f
0
0
1
1
0
1
1
0
A
0
0
1
1
C
{
0
1
C
C’
B
0
1
0
1
f
0
1
C
C’
4-to-1
MUX
A
B
f
CSI-2111 Structure of Computers I
page 5-15
Synthesis with too small MUX *
= m (0, 4, 5, 9, 13, 14, 15)
 3 solutions, according to what is
required:
A’
 f(A,B,C,D)
D’
0
1
0
D
0
D
1
8-to-1
MUX
C’D’
C
C’D
f C+D
4-to-1
MUX
A
B
f
A
0
0
A’
1
A
A
8-to-1
MUX
B C D
A B C
f
CSI-2111 Structure of Computers I
page 5-16
Complex Multiplexers
 It
is possible to design multiplexers
much more complex for particular uses:
– Multiplexers of more than one bits
– Multiple multiplexers
– Multiplexers designed using smaller
multiplexers (economy?)
CSI-2111 Structure of Computers I
page 5-17
Demultiplexers

It distributes the bit E (or the word) to one of
the 2n possible destinations (specified by S).
S1
0
0
1
1
S0
0
1
0
1
D0
E
0
0
0
D1
0
E
0
0
D2
0
0
E
0
D3
0
0
0
E
E
0
D0
E DEMUX
1
D1
2
D2
21
20
3
D3
S1
S0
1 to 4
CSI-2111 Structure of Computers I
page 5-18
5.6 Three technologies of
programmable logic
Inputs
Fixed AND
array (decoder)
Connections
Programmable
Outputs
programmable
OR array
a) (Programmable) Read-Only Memory — (P)ROM
Inputs Connections
programmable
Fixed OR
array
Outputs
Programmable
OR array
Outputs
Programmable
AND array
b) Programmable Array Logic (PAL)
Inputs
Connected
programmable
Programmable
AND array
Connections
programmable
c) Programmable Logic Array (PLA)
CSI-2111 Structure of Computers I
page 5-19
ROM (Read-Only Memory)

Circuit made up of a matrix of registermemory for storing a fixed length information
permanently.
k
inputs
(adresses)
ROM
..
.
2 k registers
of n bits
.. .
n
outputs
(data)
CSI-2111 Structure of Computers I
page 5-20
Synthesis with ROM


Any set of boolean functions f1(x1, x2…, xk) …
fn(x1, x2…, xk) can be implemented using
(2k  n) ROM and one level of programming.
Example:
I1
I0
21
20
2x4
decoder
0
1
2
3
00
01
10
11
f1(I1, I0) = Sm (1, 2, 3),
f2(I1, I0) = Sm (0, 2),
4x2 ROM
f1
f2
CSI-2111 Structure of Computers I
page 5-21
Synthesis with ROM *

Alternative representation of the solution:
= fuse intact
I1
21
I0
20
Decoder
2x4
0
1
2
3
00
01
10
11
f1(I1, I0) = Sm (0, 3)
f2(I1, I0) = (I1 + I0)'
f3(I1, I0) = PM (1)
f1
– The OR gates have all 4 entries nevertheless!
f2
f3
CSI-2111 Structure of Computers I
page 5-22
5.7 PLA
(Programmable Logic Arrays)

Programmable logic arrays are made of:
 One
layer of product terms (AND gates)
 One layer of sum terms (OR gates)
 Three layers with inverter/fuses
 Fuses in each layer are programmed
n
inverters
n
inputs
nxk
fuses
nxk
fuses
m
fuses
k
product terms
(AND gates)
kxm
fuses
m
sum terms
(OR gates)
m
inverters
m
outputs
CSI-2111 Structure of Computers I
page 5-23
Synthesis with PLA *

Example
F1(A,B,C) = Sm(3, 5, 6, 7)
 F2(A,B,C) = Sm(0, 2, 4)
 Which are the terms produced of F1 , F2 , F1’ and F2’ ?

F1(A,B,C) = AB + AC + BC
F1’ (A,B,C) = A’B’ + A’C’+ B’C’
F2 (A,B,C) = A’C’+ B’C’
F2’ (A,B,C) = AB + C
F1 & F2 = 5 terms
F1 & F2’ = 4 terms
F1’ & F2 = 3 terms
F1’ & F2’ = 5 terms
CSI-2111 Structure of Computers I
page 5-24
Synthesis with PLA *

Example
= Sm(3, 5, 6, 7) = (A’B’ + A’C’+ B’C’)’
 F2(A,B,C) = Sm(0, 2, 4) = A’C’ + B’C’
 The product terms are A’B’, A’C’ and B’C’
 F1(A,B,C)
Programming
Term
0=
complementary
1 = normal
- = unused
Number
of terms
A
Inputs
B C
1 = used
- = unused
Outputs
F1
F2
T/C
T = just as it is
C=
complementary
CSI-2111 Structure of Computers I
page 5-25
Synthesis with PLA *

Example
= Sm(3, 5, 6, 7) = (A’B’ + A’C’+ B’C’)’
 F2(A,B,C) = Sm(0, 2, 4) = A’C’ + B’C’
 The product terms are A’B’, A’C’ and B’C’
 F1(A,B,C)
Programming
Terms
A’B’
A’C’
B’C’
Number
of terms
1
2
3
4
5
A
0
0
—
Inputs
B C
0 —
— 0
0
0
Outputs
F1
F2
1
—
1
1
1
1
C
T
T/C
CSI-2111 Structure of Computers I
page 5-26
Synthesis with PLA *
A
B
C
1
A’B’
2
A’C’
3
B’C’
C C’ B B’ A A’
F1 ’
F2
F1
F2
CSI-2111 Structure of Computers I
page 5-27
5.8 PAL
(Programmable Array Logic)

Programmable logic networks made of:
 One
layer of product terms (AND gates)
 One layer of sum terms (OR gates)
 Programmable fuses with the 1st layer
 More simplistic than the PLA, but less flexible
n
inverters
n
inputs
nxk
fuses
nxk
fuses
k
product terms
(AND gates)
m
SUM terms
(OR gates)
m
outputs
CSI-2111 Structure of Computers I
page 5-28
5.9 ALU (Arithmetic and Logic
Unit)
A
Arithmetic
B
Logic
Shift
DEMUX
MUX
State (Status)
F
A
B
C
A
B
C
ALU
S
S
G
Control
G
CSI-2111 Structure of Computers I
page 5-29
Shift/Rotation and Status Bits
 Shift/rotation
of a word of several
bits via ALU.
 Status bits updated by ALU
–
–
–
–
C: Carry
V: Overflow Indicator
Z: Zero
N: Negative value
 Example:
A
Logic of the
conditions
Z = (F0  F1  ...  Fn-1)
X N Z V C
S
B
F
CSI-2111 Structure of Computers I
page 5-30
Complementary readings
 In
Mano and Kime:
– Sections 3.1 to 3.5
 Combinational
(3.3)
circuits, except Logic Simulation
– Section 3.7
 Multiplexers
– Sections 6.6 to 6.9
 Programmable
logic, ROM, PLA, PAL
– Sections 7.7 to 7.8
 Arithmetic
logic unit, shifter