Transcript TEAM FRONT END

TEAM FRONT END
ECEN 4243
Digital Computer Design
What is MIPS?
• MIPS : Microprocessor without
Interlocked Pipelined Stages developed
in 1981
• Reduced Instruction Set Computing
(RISC)
• Can be single cycle or pipelined
– We will be developing a 5 pipeline version
2
5 Stage Pipeline
3
Pipelined Datapath
4
Who is the Front End?
Team Member
Role
Rashmi Wadhwa
Team Leader
Alex Whiteway
Lead Engineer
Carolina Arbona
Wiki Specialist
Rory Little
Intra Team Relations
Phillip Walker
Researcher
Ran Liao
Production Line Principal
Ameen Alsharan
Report Compiler
Tuan Phan
Minutes of meeting(s)
5
What is the Front End?
• The Front End is the first section that an
instruction traverses on its way through
the pipeline
• Made up of two pipeline stages
– Instruction Fetch
– Instruction Decode
6
Front End Stages: IF/ID
7
Fetch
Instruction Fetch
• Pulls an instruction from memory
• Updates the PC based on the PCSrc control line
8
Front End Stages: ID
9
Decode
Instruction Decode
• What’s in a MIPS Decode stage?
– Definitely no decoding like x86
• Register File
• Sign Extend
• Register Destination Mux
10
Read Ports
• Input:
– Two Addresses: RR1 & RR2
• Each 5 bit bus determines what register will
show on its respective read port
• Asynchronous Reading
• Output:
– Two data outputs: RD1 & RD2
• 32 bit register contents sent to execution
• Data is chosen from multiplexers using RS
and RT as the respective control lines
11
Write Port
• Input
– Write Address
• 5 bit address input from WB Stage goes into
a 5 to 32 decoder
– Write Data
• 32 bit word from WB Stage
– Write Enable
• ANDed with decoder output so only 1
register is written
• Tells register that Write Address specifies to
write the data on the negative edge
12
Summary
• Write Address (WA) is the input to the 5 to 32
decoder
• Write Enable (WE) ANDed with the output of the
decoder and is the clock for the register
• Write Data (WD) is the data input to the registers
• Read Data 1 (RD1) is the 32 bit output of the
mux controlled by RR1
• Read Data 2 (RD2) is the 32 bit output of the
mux controlled by RR2
• The inputs for the muxes are all of the registers
(32 32 bit registers, 1024 total in the register file)
• Asynchronous reads and synchronous writes
13
What is in a Register File?
14
Note: Register 0 will be hard wired to always have the value 0
Other Components
• 16 to 32 bit sign extender
– Copies bit 15 to bits 16 through 31
– Immediate values need to be 32 bits for ALU
• Reg Write Mux
– Different types of instructions need to store to
registers in different parts of the instruction
– R-Type writes to $rd
– I-Type writes to $rt
– J-Type writes to $ra
15
Questions?
16