Transcript Wireless Local Area Network Design Issues Suchitav Khadanga

Wireless Local Area
Network
Design Issues
Suchitav Khadanga
RFIC Design Flow
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System Level Specification
System Analysis and Architecture Choice
Chip Set Partitioning and Chip Level Specification
Preliminary RFIC Design topology Trade off
Detailed Design Phase
RFIC Layout
Parasitic Extraction and Re simulation
Fabrication
Evaluation to Specification
System Level Specification
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System Level Specification
System Analysis and Architecture Choice
Chip Set Partitioning and Chip Level Specification
Preliminary RFIC Design topology Trade off
Detailed Design Phase
RFIC Layout
Parasitic Extraction and Re simulation
Fabrication
Evaluation to Specification
Transreceiver Architecture
 Superheterodyne Low IF down converter or
Direct Conversion Zero IF architecture
 Synthesizer with an on chip VCO
 Separate chip for Power Amplifier
Phase Noise of Synthesizer
 Depends primarily on the VCO
 VCO Phase noise suffers from the Low Q of
on chip inductors
 Off chip passives can be used to improve
the phase noise performance
Choice of Process Technology
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CMOS
Bi-CMOS
SiGe
or any other
LAYOUT
 Impedance Mismatch
 Metal Lines are Transmission Lines
Challenges
 Taking care of on chip parasitics
 Providing separate grounding for RF
Analog and digital portions to avoid
noise and crosstalk problems
 Integration of RF and Digital leads
to EMI/EMC problems
Thanks