Transcript Induced Gate Noise in Charge Detection Instrumentation Division

Induced Gate Noise in Charge Detection
Veljko Radeka, Sergio Rescia, Gianluigi De Geronimo
Instrumentation Division, Brookhaven National Laboratory, Upton, NY
Charge detection - capacitive signal source:
Drain current noise:
Induced gate noise:
2
i gn
  4kTg g

2
i gn
develops on C in  C det  C gs  C stray a noise voltage:
2
i gn

4
3
1
Cin 
2
gg 
1 C gs 
5
gdo
 3
1   C gs 
 4kT


gdo 5  C in 
With a capacitive signal source induced noise voltage spectrum is white → both drain and
gate noise can be referenced to the gate as an equivalent series noise resistance.
Neglecting correlation :
  
1 
Req 
gdo  5

2
C
 gs  

 
 Cin  
;
2

 0.4
5
For power optimized CMOS: Cgs≤(1⁄4)Cin , and the increase in Req is < 2.5%.
The effect of correlation is less than ~10%.
(Ref. 3)
2
2
Real Term in the Gate Admittance
jC gs
1
1
Z g  Ri 
 Yg 

 jC gs  (C gs )2 Ri
jC gs
Z g 1  jC gs Ri
1 (C gs )
1 f 
2
2
Re(Yg )  g g  (C gs ) Ri 
 
g


gdo


 do
e
5 gdo
5  fT 
2
2
unity gain frequency
For: f fT  1 4 , gdo  gms
gg 
1
gms
80
electron transit time
(for f fT  1)
Real (“Damping”) Term in the Control Electrode Admittance of all
Charge Controlled Devices
transit time
Charge in transport:
q  id e
Transconductance: gm  did dv g   dq dv g  1  e   C g  e
Unity gain frequency:
T  2 fT  gm C g  1  e
Control electrode admittance: Yg  jC g  j e gm
At high frequencies:
gm  j   gm exp   ja e   gm 1  ja e 
Yg  jC g  a gm  e 
2
phase shift
g g =a gm  e   a gm  f fT   a C g 
2
a«1 ;
phase shift
2
2
 1 5 in CMOS
Damping of tuned circuits by control electrodes
with zero dc current observed in 1930’s (Ref. 1)
gm
Gate Induced Noise vs f and fT
NF=1dB
0.25dB
fT(GHz)
10
330
8
14
220
16
18
140
26
23
90
45
28
68
 ≈ 4/3
 ≈ 2/3
i
1 f 2
1
2 1
 4kT  ( ) gm  4kT  ( C gs )
5 fT
5
gm
Cgs(fF)
4
Long L
2
gn
gm(mS)
Short L
(<3?)
<1.2
Data from: C.-H. Chen,et al., IEEE
Trans. Electron devices,48, 2884(Dec. 2001)
Noise Enhancement with VDS in DSM MOSFETS?
Drain current thermal noise vs VDS
Gate current noise vs VDS
No significant enhancement at L=0.18 mm !
From: A. J. Scholten et al., IEEE Trans.
Electron Devices, 50, 618 (March 2003)
“White noise gamma factor” vs VDS and L
Gradual channel
region
Velocity saturation
region
Noise model: Channel
Length Modulation (CLM)
2/3 ≤  < 1.1
From: C.-H. Chen and M. J. Deen,
IEEE Trans. Electron Devices, 49,
1484(Aug. 2002)
Equivalent Series Noise Resistance for Charge Detection (Capacitive Source)
Transconductance=
gms  gdo
Req
 gms

 1
5
2
 C gs  1
 C gb 
gmb 1
  Rb gms  

   Rg gms    Rb gmb 

C

g

C
ms
 in 
 in 
Gate induced
Intrinsic channel noise
«1
Gate
resistance
Induced into gate
Substrate
resistance
(shielded by the
inversion layer!?)
Ref.: 9
2
9
Acknowledgements
Numerous discussions with Anand Kandasamy, Paul
O’Connor and Pavel Rehak are gratefully acknowledged.
References
1.
Ferris, W. R., Proc. IRE, 24, No. 1 (1936) 82
2.
Van der Ziel, A., Proc. IEEE, 51 (1963) 461
3.
Radeka, V., IEEE Trans. Nucl. Sci., NS-11 (1964) 358
4.
Manku, T., IEEE Journal of Solid-State Circuits, 34, No. 3 (1999) 277
5
Signoracci, L., et al., Solid-State Electronics, 45 (2001) 205
6.
C.-H. Chen, et al., IEEE Trans. Electron Devices, 48, (Dec. 2001) 2884
7.
C.-H. Chen and M.J. Deen, IEEE Trans. Electron Devices,
49, (Aug. 2002) 1484
8.
A. J. Scholten, et al., IEEE Trans. Electron Devices, 50, (March 2003) 618
9.
S. V. Kishore, et al., IEEE 1999 Custom Integrated Circuits Conference, p.365