Transcript Document 7694226

ARM7TDMI Processor
ARM7TDMI processor
• The ARM7TDMI processor : 32-bit 범용 microprocessor중
Advanced RISC machine 계열 중 하나
• ARM7TDMI 가 뭐냐?
ARM7 - 32-bit Advanced RISC Machine
T - Thumb architecture extension
• Two separate instruction sets, 32-bit ARM instructions and 16-bit Thumb
instructions
D - Debug extension
M - Enhanced multiplier
I - Embedded ICE macrocell extension
•
ARM{x}{y}{z}{T}{D}{M}{I}{E}{J}{-S}
x:제품군, y:MMU/MPU z:캐시 D:JTAG debug M: 곱셈기
I: embeddedICE Macrocell E: dsp 확장 J: jazelle
F: VFP S: synthesizible버전
2
ARM7TDMI Block Diagram
•
폰 노이만 아키텍쳐
•
3-단 파이프라인
– fetch, decode, execute
•
32-bit 데이터 버스(core)
•
32-bit 어드레스 버스(core)
•
37 32-bit 레지스터
•
32-bit ARM instruction set
•
16-bit THUMB instruction set
•
32x8 Multiplier(곱셈기)
•
Barrel Shifter(배럴 시프트)
3
ARM7TDMI 동작 모드(1)
•
ARM7TDMI 프로세서 2가지 동작 상태(모드):
– ARM 모드 : executes 32-bit, word aligned ARM instructions
– THUMB 모드: execute 16-bit, halfword aligned THUMB instructions
• Switching state
– THUMB 모드 진입
• BX 명령어에서 operand register 0번 bit의 상태로 구분(set)
• Automatically on return from an exception (IRQ, FIQ, ABORT, SWI,…), if
the exception was entered with the processor in THUMB state.
– ARM 모드 진입
• BX 명령어에서 operand register 0번 bit의 상태(clear)
• Automatically on the processor taking an exception. In this case, the PC
is placed in the exception mode’s link register.
4
메모리에서 명령어 읽기
명령어 길이
8bit
메모리
(bus width)
16bit
메모리
(bus width)
32bit
메모리
(bus width)
ARM 32bit
4사이클
2사이클
1사이클
Thumb 16bit
2사이클
1사이클
1사이클
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ARM7TDMI 동작 모드(2)
• ARM7TDMI 7가지 모드 지원:
–
–
–
–
–
–
–
User (usr): 일반적인 ARM 프로그램 실행상태
FIQ (fiq): 고속 인터럽트 처리
IRQ (irq): 일반 인터럽트 처리
Supervisor (svc): 운영체제를 위한 보호 모드
Abort mode (abt): 가상메모리와 메모리 보호 처리
System (sys): 운영체제를 위한 user 모드
Undefined (und): 하드웨어 코프로세서의 소프트웨어 에뮬레이션
• 모드 전환은 외부 인터럽트나 익셉션 처리를 위해 사용됨
– 대부분의 어플리케이션은 user mode에서 실행
– 그 밖에는 인터럽트, exception, protect된 리소스의 접근을 위해
system 모드가 사용됨.
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ARM7TDMI Registers
• ARM7TDMI 총 37개 register:
– 31 general-purpose 32-bit registers
– 6 status registers(CPSR, SPSR_SVC, SPSR_adt, …)
• 이 37개 register들은 한번 볼 수는 없다.(visible 16개)
– The processor state and operating mode dictate which registers are
available to the programmer.
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ARM State Registers Set
8
THUMB State Registers Set
9
Relationship between ARM and
THUMB state registers
• The THUMB state registers relate to the ARM state registers
in the following way:
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Program Status Registers (1/3)
• ARM7TDMI 한 개의 Current Program Status Register
(CPSR), 과 5개의 exception handler를 위해 Saved Program
Status Registers (SPSRs)
• These register's functions are:
– 가장 최근에 실행된 ALU 동작에 대한 정보를 저장
– interrupt enable/disable 제어
– 프로세서의 동작모드 설정
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Program Status Registers (2/3)
• Condition Code Flags
–
–
–
–
N : negative/less than flag 연산 결과가 마이너스인 경우 셋
Z : zero flag 연산결과가 0이 되었을 때 셋
C : carry/borrow/extend flag 자리올림/내림발생 및 shift 연산에 사용
V : overflow 발생 시 사용
• In ARM state, all instructions may be executed conditionally.
• In THUMB state, only the Branch instruction is capable of conditional
execution.
• Control Bits
– The I, F, T and M[4:0]) bits will be changed when an exception
arises. If the processor is operating in a privileged mode, they can
also be manipulated by software.
– T bit:
• 동작모드상태, 셋 되면 thumb모드 동작, 외부 signal에 의해서도 발생
• CPSR에 강제로 이 bit를 바꾸면 예측하지 못하는 상태로 들어갈 수 있다.
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Program Status Registers (3/3)
• Control Bits
– Interrupt disable bits:
• I 와 F bit Interrupt disable bit다. Set되었을 때 IRQ/ FIQ interrupt를
disable시킨다.
– Mode bits:
• The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits.
• processor's operating mode를 결정한다.
• 잘못된 값을 설정하면, processor 가 reset 되거나 복구 불능상태에
빠진다.
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Exceptions (1/5)
• Exception program이 halt되었을 때 일반적으로 발생한다.
– For example to service an interrupt from a peripheral.
• ARM 7 가지의 exception과 각각의 processor mode마다
exception을 가진다.
• ARM Exception vectors
Address
Exception
Mode in Entry
0x00000000
Reset
Supervisor
0x00000004
Undefined instruction
Undefined
0x00000008
Software Interrupt
Supervisor
0x0000000C
Abort (prefetch)
Abort
0x00000010
Abort (data)
Abort
0x00000014
Reserved
Reserved
0x00000018
IRQ
IRQ
0x0000001C
FIQ
FIQ
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Exceptions (2/5)
• When handling an exception, the ARM7TDMI:
–
–
–
–
–
–
–
–
–
Link Register에 다음 수행될 명령어의 주소를 저장한다.
SPSR에 현재의 CPSR값을 복사한다.
Exception 에 따른 값을 CPSR로 가져온다.
Exception verctor로부터 fetch된 다음명령어를 PC로 가져온다.
여러가지 다른 exception들로 부터 방해를 막기위해 인터럽트
disable flag을 set해야 한다.
THUMB 모드에서 exception이 발생하면, pc가 exception vector를
읽어 올때 ARM mode로 자동적으로 바뀌게 된다.
저장된 Link Register에서 – offset(exception vector) 만큼 뺀값을
pc에 저장.
저장된 SPSR을 CPSR에 복사
인트럽트 disable flag를 clear 한다.(인트럽트가 set되어 있었다면)
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Exceptions (3/5)
• Reset
– When the processor’s Reset input is asserted
• CPSR  Supervisor + I + F
• PC  0x00000000
• Undefined Instruction
– If an attempt is made to execute an instruction that is undefined
• LR_undef  Undefined Instruction Address + #4
• PC  0x00000004, CPSR  Undefined + I
• Return with : MOVS pc, lr
• Prefetch Abort
– Instruction fetch memory abort, invalid fetched instruction
• LR_abt  Aborted Instruction Address + #4, SPSR_abt  CPSR
• PC  0x0000000C, CPSR  Abort + I
• Return with : SUBS pc, lr, #4
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Exceptions (4/5)
• Data Abort
– Data access memory abort, invalid data
• LR_abt  Aborted Instruction + #8, SPSR_abt  CPSR
• PC  0x00000010, CPSR  Abort + I
• Return with : SUBS pc, lr, #4 or SUBS pc, lr, #8
• Software Interrupt
– Enters Supervisor mode
• LR_svc  SWI Address + #4, SPSR_svc  CPSR
• PC  0x00000008, CPSR  Supervisor + I
• Return with : MOV pc, lr
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Exceptions (5/5)
• Interrupt Request
– Externally generated by asserting the processor’s IRQ input
• LR_irq  PC - #4, SPSR_irq  CPSR
• PC  0x00000018, CPSR  Interrupt + I
• Return with : SUBS pc, lr, #4
• Fast Interrupt Request
– Externally generated by asserting the processor’s FIQ input
•
•
•
•
LR_fiq  PC - #4, SPSR_fiq  CPSR
PC  0x0000001C, CPSR  Fast Interrupt + I + F
Return with : SUBS pc, lr, #4
Handler @0x1C speeds up the response time
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ARM Instruction Set
Summary
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Condition Field (1/2)
• All ARM instructions can be conditionally executed, which
means that their execution may or may not take place
depending on the values of values of the N, C, C and V flags
in the CPSR
• Every instruction contains a 4-bit condition code field in bits
31 to 28
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Condition Field (2/2)
• 15개의 condition이 있고, 명령어의 mnemonic에 2개의 접미사가
붙는다.
• Assembley에서 Branch 명령의 경우 z-flag가 set되면, BEQ가
된다.
• B initReset
• 0xEA00000F
Code
Suffix
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
EQ
NE
CS
CC
MI
PL
VS
VC
HI
LS
GE
LT
GT
LE
AL
Flags
Z set
Z clear
C set
C clear
N set
N clear
V set
V clear
C set and Z clear
C clear or Z set
N equals V
N not equal to V
Z clear AND (N equals V)
Z set OR (N not equal to V)
(ignored)
Meaning
Equal
Not equal
Unsigned higher or same
Unsigned lower
Negative
Positive or zero
Overflow
No overflow
Unsigned higher
Unsigned lower or same
Greater or equal
Less than
Greater than
Less than or equal
always
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Branch Instructions (1/2)
•
모든 ARM Processors branch 명령어의 condition을 가질 수 있고, 최대
앞 뒤로 32Mbyte만큼 분기 할 수 있다. (0-24bit: 25개 0x1ffffff)
– As the Program Counter (PC) is one of the general-purpose registers
(register 15), a branch or jump can also be generated by writing a value to
register 15.
•
subroutine call도 표준 branch중 한 변형이다. Branch후에는 항상
r14(lr)에 명령어의 어드레스를 항상 저장해야 한다.
•
load 명령어는 4Gbyte어드레스 영역의 어떤 곳이라도 분기할 수 있다.
메모리로 부터 로드 된 32bit 값은 pc에 들어가 branch을 일으킨다.
•
The ARM7TDMI processor that support the Thumb instruction set
also support a branch instruction (BX) that jumps to a given
address, and optionally switches executing Thumb instructions.
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Branch Instructions (2/2)
•
List of branch instructions
B, BL
BX
•
func
Branch, and branch with link
Branch and exchange instruction set (ARM모드에서 Thumb모드로 전환)
Examples
B
BCC
label
label
; branch unconditionally to label
; branch to label if carry flag is clear
BEQ
label
; branch to label if zero flag is set
MOV PC, #0
; R15 = 0, branch to location zero
BL
; subroutine call to function
func
MOV PC, LR
MOV LR, PC
LDR PC, =func
; R15=R14, return to instruction after the BL
; store the address of the instruction after the next one into R14
; load a 32-bit value into the program counter
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Data Processing (1/2)
•
ARM은 16개의 data processing instructions. 대부분의 data
processing instruction은 2개의 operand를 가진다. (Move 와and
Move 은 하나의operand만 가진다.)
•
하나의 register에 하나의 결과값을 저장한다. ( Compare 와 Test명령은
제외-condition code로 업데이트함. 결과를 저장하지 않는다.)
– 두개의 operand중 하나는 항상 register고, 나머지는 shitfer
operand다.(그밖에 즉치나 register값이다.가 올 수도 있다.)
– ALU가 operand2로 사용하기 전에 shifter후에 operand로 사용할 수 있다.
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Data Processing (2/2)
• List of data processing instructions
Assembler Mnemonic
OP Code
AND
EOR
WUB
RSB
ADD
ADC
SBC
RSC
TST
TEQ
CMP
CMN
ORR
MOV
BIC
MVN
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Action
Operand1 AND operand2
Operand1 EOR operand2
Operand1 – operand2
Operand2 operand1
Operand1 + operand2
Operand1 + operand2 + carry
Operand1 – operand2 + carry –1
Operand2 – operand1 + carry –1
As AND, but results is not written
As EOR, but result is not written
As SUB, but result is not written
As ADD, but result is not written
Operand1 OR operand2
Operand2 (operand1 is ignored)
Operand1 AND NOT operand2 (Bit clear)
NOT operand2 (operand1 is ignored)
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곱셈 명령어들 (1/2)
• ARM은 2가지 형식의 곱셈명령어가 있다.
– normal, 32-bit result
– long, 64-bit result
• 곱셈명령어는 항상 입력으로 두개의 operand register를 가진다.
• For example)
MUL
MULS
MLA
R4, R2, R1
R4, R2, R1
R7, R8, R9, R3
; Set R4 to value of R2 multiplied by R1
; R4 = R2xR1, set N and Z flags
; R7 = R8xR9 + R3
일반적으로 normal 연산에서 결과값은 항상 하위 값만 가진다.
27
곱셈 명령어들 (2/2)
•
64bit의 결과를 위해서는 4개의 곱셈 명령이 있다. (long 곱셈)
– 2개의 값을 곱해서 상위와 하위로 나누어서 각각 저장한다.
SMULL
UMULL
UMLAL
R4, R8, R2, R3 ; R4 = bits 0 to 31 of R2xR3
; R8 = bits 32 to 63 of R2 x R3
R6, R8, R0, R1 ; R6, R8 = R0 x R1
R5, R8, R0, R1 ; R5, R8 = R0 x R1 + R5, R8
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Load / Store 명령어 (1/2)
• Load/ store 명령어는 3가지 타입이 있다.
– load / store 하나의 register값을 갖는다.
– load / store multiple register values
– swap a register value with the value of a memory location
• load / store 하나의 register값을 갖는다
–
–
–
–
–
LDR/STR, Load/Store word
LDRB/STRB, Load/Store byte
LDRH/STRH, Load/Store unsigned halfword
LDRSB, Load signed byte
LDRSH, Load signed halfword
29
Load / Store 명령어들 (2/2)
• Load and Store multiple registers
– List of load and store multiple instructions
• LDM, Load multiple
• STM, Store multiple
– STMDB
SP!, {R0,R4,R5,R6,LR}
• Swap a register value with the value of a memory location
– List of semaphore instructions
• SWP, Swap
• SWPB, Swap Byte
– SWP R12, R10, [R9]
– SWPB
R3, R4, [R8]
; load R12 from address R9 and
; store R10 to address R9
; load byte to R3 from address R8 and
;store byte from R4 to address R8
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SWI : Software Interrupt
• The Software Interrupt instruction enters supervisor mode
– ARM에서는 swi를 거의 사용하지 않는다. 대표적으로 사용하는 것은
JTAG 에뮬레이터를 사용하기 위해서 사용된다.
• Semihosting library 호출시
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THUMB Instruction Set
Summary
33
Thumb 어떻게 동작할까 ?
• Thumb 명령어는 ARM명령어의 파생 계열이다.
– Optimized for code density.
• 대부분의 Thumb instruction은 ARM instruction:
– ADD Rd, #Offset8 <> ADDS Rd, Rd, #Offset8
• Inline expansion of Thumb Instruction to ARM Instruction
– Real time decompression
– Thumb instructions are not actually executed on the core
• The core needs to know whether it is reading Thumb
instructions or ARM instructions.
– Core has two execution states - ARM and Thumb
– Core does not have a mixed 16 and 32 bit instruction set.
34
Thumb Instruction Set Decompression
THUMB: ADD Rd,#Constant
15
0
001
Always
condition
31
1110
10
Major
opcode
28
Minor
opcode
24
00 1
Rd
Constant
Destination &
source register
21 20 19
0100 1
0
16 15
Rd
0
Zero extended
constant
12
Rd
11
0000
8
7
0
Constant
I op1+op2 S
ARM: ADDS Rd, Rd, #Constant
35
Branch 명령어들
• Thumb supports four types of branch instruction:
– unconditional branch =>전후 2Kbytes(2^11)
– conditional branch =>전후 256 bytes (2^8)
• List of branch instructions
–
–
–
–
B
B
BL
BX
conditional branch
unconditional branch
Branch with link
Branch and exchange instruction set
36
Data Processing 명령어들
• Thumb data-processing instruction은 ARM data-processing
instruction의 축약이다.
– 모든 Thumb data-processing instructions set the condition codes
• List of data-processing instructions
–
–
–
–
–
–
–
–
–
–
ADC, Add with Carry
ADD, Add
AND, Logical AND
ASR, Arithmetic shift right
BIC, Bit clear
CMN, Compare negative
CMP, Compare
EOR, Exclusive OR
LSL, Logical shift left
LSR, Logical shift right
–
–
–
–
–
–
–
–
–
MOV, Move
MUL, Multiply
MVN, Move NOT
NEG, Negate
ORR, Logical OR
ROR, Rotate Right
SBC, Subtract with Carry
SUB, Subtract
TST, Test
37
Load / Store Register 명령어들
• Thumb에서는 8가지의 load / store register 명령어들
• List of load and store register instructions
–
–
–
–
–
–
–
–
LDR
LDRB
LDRH
LDRSB
LDRSH
STR
STRB
STRH
Load word
Load unsigned byte
Load unsigned halfword
Load signed byte
Load signed halfword
Store word
Store byte
Store halfword
38
Load / Store 곱셈 명령어들
• Thumb에서는 4가지 load / store 곱셈 명령어
• 2개의 block copy (a load and store)
• 나머지 2개는 스택명령어인 PUSH / POP 이다.
• 스택명령어는 full descending stack동작만 지원한다.
stack pointer는 base register로 사용된다.
• List of load and store multiple instructions
–
–
–
–
LDM
POP
PUSH
STM
Load multiple
Pop multiple
Push multiple
Store multiple
39
ARM vs THUMB
Code size
• Generally, routines in THUMB code are between 65 and 70%
the size of the equivalent ARM code.
60%
65%
% of ARM code size
70%
75%
41
Code performances vs Memory width
42
Arm Instruction Set Advantages
• All instructions are 32 bits long.
• Most instructions are executed in one single cycle.
• Every instructions can be conditionally executed.
• A load/store architecture
– Data processing instructions act only on registers
• Three operand format
• Combined ALU and shifter for high speed bit manipulation
– Specific memory access instructions with powerful auto-indexing
addressing modes
– 32 bit ,16 bit and 8 bit data types
– Flexible multiple register load and store instructions
43
Thumb Instruction Set Advantages
• All instructions are exactly 16 bits long to improve code density
over other 32-bit architectures
• The Thumb architecture still uses a 32-bit core, with:
–
–
–
–
32-bit address space
32-bit registers
32-bit shifter and ALU
32-bit memory transfer
• Gives....
– Long branch range
– Powerful arithmetic operations
– Large address space
44