Transcript Example Cycle 0

Tomasulo algorithm
윤진훈
Tomasulo algorithm ?
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동적 스케쥴링
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–
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Reservation station : 이슈를 기다리는 명령들의 오퍼랜드를 저장하는 버퍼
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–
–
–
–
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RAW 해저드 : 브로드캐스트를 활용, 오퍼랜드를 사용가능 하자마자 실행
WAR, WAW 해저드 : 레지스터 리네이밍 기법 사용
Op : 연산
Qj, Qk : 예약 스테이션
Vj, Vk : 소스 오퍼랜드의 값
Busy : 사용 가능 여부
A : 메모리 주소 계산에 필요한 정보 저장
명령어 진행 과정
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–
–
Issue
Execute
Write result
Tomasulo algorithm
Broadcast
FP Register
Instruction Queue
ADD
LOAD
MUL
SUB
DIV
ADD
STORE
ADD
F0,
F1,
F3,
F6,
F8,
F2,
F8,
F1,
F1, F2
[R1]
F5, F0
F3, F10
F9, F2
F6, F9
[R1]
F3, F4
1 FIFO
Read Value 3
Issue
Opcode
2
Operand 4
Write Result
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
Value
Value
Value
Value
Value
Value
Value
Value
Value
Value
Value
F10
LOAD
ADD
MUL
SUB
DIV
ADD
STORE
ADD
Broadcast
7
Reservation Station
RS ALU
8
7
RS MUL
RS LD/ST
Execute
5
Execute
ALU 0
ALU 1
MUL 0
MUL 1
LD 0
Out of order
ST 0
6 Write CDB
Common data bus
F1,
F0,
F3,
F6,
F8,
F1,
F8,
F2,
[R1]
F1, F2
F5, F0
F3, F10
F9, F2
F3, F4
[R1]
F6, F9
Example Source
•
실행 사이클
–
–
–
–
–
–
•
L/S
ADD, SUB
MUL
DIV
Bypass
Broadcast
1사이클
2사이클
4사이클
10사이클
1사이클
1사이클
우선순위
–
LOAD → STORE → DIV → MUL → SUB → ADD
Example Cycle 0
Instruction status
ADD
F0, F1, F2
LOAD
F1, [R1]
MUL
F3, F5, F0
SUB
F6, F3, F10
DIV
F8, F9, F2
ADD
F2, F6, F9
STORE
F8, [R1]
ADD
F1, F3, F4
IS
EX
WR
Op
Vj
Vk
Reservation Station
Time
Name
Busy
ALU 0
Qj
Qk
Name
Busy
N
LD 0
N
ALU 1
N
ST 0
N
MUL 0
N
MUL 1
N
F7
F8
Address
Register result status
clock
F0
F1
F2
F3
F4
F5
F6
F9
F10
Example Cycle 1
Instruction status
IS
ADD
F0, F1, F2
1
LOAD
F1, [R1]
MUL
F3, F5, F0
SUB
F6, F3, F10
DIV
F8, F9, F2
ADD
F2, F6, F9
STORE
F8, [R1]
ADD
F1, F3, F4
EX
WR
1. 명령어 큐에서 명령어를 꺼낸다.
2. RS 상태 확인 후 Op를 입력한다.
3. 레지스터로부터 Operand를 읽어온다.
Reservation Station
Time
Name
Busy
Op
Vj
Vk
ALU 0
Y
ADD
R(F1)
R(F2)
ALU 1
N
MUL 0
N
MUL 1
N
Qj
Qk
Name
Busy
LD 0
N
ST 0
N
F7
F8
Address
Register result status
clock
F0
1
ALU 0
F1
F2
F3
F4
F5
F6
F9
F10
Example Cycle 2
Instruction status
IS
EX
ADD
F0, F1, F2
1
2
LOAD
F1, [R1]
2
MUL
F3, F5, F0
SUB
F6, F3, F10
DIV
F8, F9, F2
ADD
F2, F6, F9
STORE
F8, [R1]
ADD
F1, F3, F4
WR
Operand가 사용가능
하므로 실행됨
Reservation Station
Time
Name
Busy
Op
Vj
Vk
ALU 0
Y
ADD
R(F1)
R(F2)
ALU 1
N
MUL 0
N
MUL 1
N
Qj
Qk
Name
Busy
LD 0
Y
ST 0
N
F7
F8
Address
[R1]
Register result status
clock
F0
F1
2
ALU 0
LD 0
F2
F3
F4
F5
F6
F9
F10
Example Cycle 3
Instruction status
IS
EX
ADD
F0, F1, F2
1
2
LOAD
F1, [R1]
2
3
MUL
F3, F5, F0
3
SUB
F6, F3, F10
DIV
F8, F9, F2
ADD
F2, F6, F9
STORE
F8, [R1]
ADD
F1, F3, F4
WR
F1은 WAR 해저드이다.
그러나 ADD에서 오퍼랜드를
이미 복사해놨기 때문에 상관
없다.
ADD의 결과값을 받아야 하는
RAW 해저드
Reservation Station
Time
Name
Busy
Op
Vj
Vk
ALU 0
Y
ADD
R(F1)
R(F2)
ALU 1
N
MUL 0
Y
MUL 1
N
MUL
R(F5)
F2
F3
Qj
Qk
Name
Busy
LD 0
Y
ST 0
N
F7
F8
Address
[R1]
ALU 0
Register result status
clock
F0
F1
3
ALU 0
LD 0
MUL 0
F4
F5
F6
F9
F10
Example Cycle 4
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
4
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
SUB
F6, F3, F10
4
DIV
F8, F9, F2
ADD
F2, F6, F9
STORE
F8, [R1]
ADD
F1, F3, F4
우선순위에 따라 LOAD 먼저 처리
ADD에서 연산이 끝나지 않았음에
도 LOAD의 결과가 나온 것에 주목
Reservation Station
Time
Name
Busy
Op
Vj
Vk
ALU 0
Y
ADD
R(F1)
R(F2)
ALU 1
Y
SUB
MUL 0
Y
MUL
MUL 1
N
R(F10)
Qj
Qk
MUL 0
R(F5)
Name
Busy
LD 0
N
ST 0
N
Address
ALU 0
실행 못함
Register result status
clock
F0
F1
4
ALU 0
M(2)
F2
F3
F4
MUL 0
레지스터에 결과값이 반영됨
F5
F6
ALU 1
F7
F8
F9
F10
Example Cycle 5
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
SUB
F6, F3, F10
4
DIV
F8, F9, F2
5
ADD
F2, F6, F9
STORE
F8, [R1]
ADD
F1, F3, F4
Vj
Vk
Reservation Station
Time
Name
Busy
Op
ALU 0
N
ALU 1
Y
SUB
MUL 0
Y
MUL
R(F5)
MUL 1
Y
DIV
R(F9)
R(F2)
F2
F3
F4
R(F10)
Qj
Qk
MUL 0
Name
Busy
LD 0
N
ST 0
N
F7
F8
Address
ALU 0
Register result status
clock
F0
F1
5
M(1)
M(2)
MUL 0
레지스터에 결과값이 반영됨
F5
F6
ALU 1
MUL 1
F9
F10
Example Cycle 6
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
SUB
F6, F3, F10
4
DIV
F8, F9, F2
5
ADD
F2, F6, F9
6
STORE
F8, [R1]
ADD
F1, F3, F4
Broadcasting에 1사이클
6
Reservation Station
Time
Name
Busy
Op
ALU 0
Y
ALU 1
Vj
Vk
Qj
ADD
R(F9)
Y
SUB
R(F10)
MUL 0
Y
MUL
R(F5)
MUL 1
Y
DIV
R(F9)
R(F2)
F4
Qk
Name
Busy
ALU 1
LD 0
N
MUL 0
ST 0
N
F7
F8
Address
M(1)
Register result status
clock
F0
F1
F2
F3
6
M(1)
M(2)
ALU 0
MUL 0
F5
F6
ALU 1
MUL 1
F9
F10
Example Cycle 7
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
SUB
F6, F3, F10
4
DIV
F8, F9, F2
5
ADD
F2, F6, F9
6
STORE
F8, [R1]
7
ADD
F1, F3, F4
Bypass에 1사이클
6
Reservation Station
Time
Name
Busy
Op
ALU 0
Y
ALU 1
Vj
Vk
Qj
ADD
R(F9)
Y
SUB
R(F10)
MUL 0
Y
MUL
R(F5)
M(1)
MUL 1
Y
DIV
R(F9)
R(F2)
F4
Qk
Name
Busy
ALU 1
LD 0
N
MUL 0
ST 0
Y
F7
F8
Address
[R1]
M(1)
Register result status
clock
F0
F1
F2
F3
7
M(1)
M(2)
ALU 0
MUL 0
F5
F6
ALU 1
MUL 1
F9
F10
Example Cycle 8
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
SUB
F6, F3, F10
4
DIV
F8, F9, F2
5
ADD
F2, F6, F9
6
STORE
F8, [R1]
7
ADD
F1, F3, F4
RS가 꽉 차서 이슈 불가능
6
Reservation Station
Time
Name
Busy
Op
ALU 0
Y
ALU 1
Vj
Vk
Qj
ADD
R(F9)
Y
SUB
R(F10)
MUL 0
Y
MUL
R(F5)
M(1)
MUL 1
Y
DIV
R(F9)
R(F2)
F4
Qk
Name
Busy
ALU 1
LD 0
N
MUL 0
ST 0
Y
F7
F8
Address
[R1]
Register result status
clock
F0
F1
F2
F3
8
M(1)
M(2)
ALU 0
MUL 0
F5
F6
ALU 1
MUL 1
F9
F10
Example Cycle 9
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
SUB
F6, F3, F10
4
DIV
F8, F9, F2
5
ADD
F2, F6, F9
6
STORE
F8, [R1]
7
ADD
F1, F3, F4
6
Reservation Station
Time
Name
Busy
Op
ALU 0
Y
ALU 1
Vj
Vk
Qj
ADD
R(F9)
Y
SUB
R(F10)
MUL 0
Y
MUL
R(F5)
M(1)
MUL 1
Y
DIV
R(F9)
R(F2)
F4
Qk
Name
Busy
ALU 1
LD 0
N
MUL 0
ST 0
Y
F7
F8
Address
[R1]
Register result status
clock
F0
F1
F2
F3
9
M(1)
M(2)
ALU 0
MUL 0
F5
F6
ALU 1
MUL 1
F9
F10
Example Cycle 10
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
SUB
F6, F3, F10
4
DIV
F8, F9, F2
5
ADD
F2, F6, F9
6
STORE
F8, [R1]
7
ADD
F1, F3, F4
6
Reservation Station
Time
Name
Busy
Op
ALU 0
Y
ALU 1
Vj
Vk
Qj
ADD
R(F9)
Y
SUB
R(F10)
MUL 0
Y
MUL
R(F5)
M(1)
MUL 1
Y
DIV
R(F9)
R(F2)
F4
Qk
Name
Busy
ALU 1
LD 0
N
MUL 0
ST 0
Y
F7
F8
Address
[R1]
Register result status
clock
F0
F1
F2
F3
10
M(1)
M(2)
ALU 0
MUL 0
F5
F6
ALU 1
MUL 1
F9
F10
Example Cycle 11
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
11
SUB
F6, F3, F10
4
DIV
F8, F9, F2
5
ADD
F2, F6, F9
6
STORE
F8, [R1]
7
ADD
F1, F3, F4
6
Reservation Station
Time
Name
Busy
Op
Vj
Vk
Qj
ALU 0
Y
ADD
R(F9)
ALU 1
Y
SUB
R(F10)
MUL 0
N
MUL 1
Y
DIV
R(F9)
R(F2)
F4
Qk
Name
Busy
ALU 1
LD 0
N
MUL 0
ST 0
Y
F7
F8
Address
[R1]
Register result status
clock
F0
F1
F2
F3
11
M(1)
M(2)
ALU 0
M(3)
F5
F6
ALU 1
MUL 1
F9
F10
Example Cycle 12
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
11
SUB
F6, F3, F10
4
DIV
F8, F9, F2
5
ADD
F2, F6, F9
6
STORE
F8, [R1]
7
ADD
F1, F3, F4
Broadcasting에 1사이클
6
Reservation Station
Time
Name
Busy
Op
Vj
Vk
Qj
ALU 0
Y
ADD
R(F9)
ALU 1
Y
SUB
R(F10)
MUL 0
N
MUL 1
Y
DIV
R(F9)
R(F2)
F4
Qk
Name
Busy
ALU 1
LD 0
N
M(3)
ST 0
Y
F7
F8
Address
[R1]
Register result status
clock
F0
F1
F2
F3
12
M(1)
M(2)
ALU 0
M(3)
F5
F6
ALU 1
MUL 1
F9
F10
Example Cycle 13
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
11
SUB
F6, F3, F10
4
13
DIV
F8, F9, F2
5
6
ADD
F2, F6, F9
6
STORE
F8, [R1]
7
ADD
F1, F3, F4
Bypass에 1사이클
Reservation Station
Time
Name
Busy
Op
ALU 0
Y
ADD
ALU 1
Y
SUB
MUL 0
N
MUL 1
Y
Vj
Vk
Qj
R(F9)
M(3)
R(F10)
DIV
R(F9)
R(F2)
F4
Qk
Name
Busy
ALU 1
LD 0
N
M(3)
ST 0
Y
F7
F8
Address
[R1]
Register result status
clock
F0
F1
F2
F3
13
M(1)
M(2)
ALU 0
M(3)
F5
F6
ALU 1
MUL 1
F9
F10
Example Cycle 14
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
11
SUB
F6, F3, F10
4
13
DIV
F8, F9, F2
5
6
ADD
F2, F6, F9
6
STORE
F8, [R1]
7
ADD
F1, F3, F4
Reservation Station
Time
Name
Busy
Op
Vj
Vk
Qj
ALU 0
Y
ADD
R(F9)
ALU 1
ALU 1
Y
SUB
M(3)
R(F10)
MUL 0
N
MUL 1
Y
DIV
R(F9)
R(F2)
F4
Qk
Name
Busy
LD 0
N
ST 0
Y
F7
F8
Address
[R1]
Register result status
clock
F0
F1
F2
F3
14
M(1)
M(2)
ALU 0
M(3)
F5
F6
ALU 1
MUL 1
F9
F10
Example Cycle 15
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
11
SUB
F6, F3, F10
4
13
15
DIV
F8, F9, F2
5
6
ADD
F2, F6, F9
6
STORE
F8, [R1]
7
ADD
F1, F3, F4
15
Reservation Station
Time
Name
Busy
Op
Vj
Vk
Qj
ALU 0
Y
ADD
R(F9)
ALU 1
ALU 1
Y
ADD
R(F3)
R(F4)
MUL 0
N
MUL 1
Y
DIV
R(F9)
R(F2)
F4
Qk
Name
Busy
LD 0
N
ST 0
Y
F7
F8
Address
[R1]
Register result status
clock
F0
F1
F2
F3
15
M(1)
M(2)
ALU 0
M(3)
F5
F6
M(4)
MUL 1
F9
F10
Example Cycle 16
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
11
SUB
F6, F3, F10
4
13
15
DIV
F8, F9, F2
5
6
16
ADD
F2, F6, F9
6
STORE
F8, [R1]
7
ADD
F1, F3, F4
15
16
Vj
SUB의 Broadcasting에 1사이클
Reservation Station
Time
Name
Busy
Op
ALU 0
Y
ADD
ALU 1
Y
ADD
MUL 0
N
MUL 1
N
R(F3)
Vk
Qj
R(F9)
M(4)
Qk
R(F4)
Name
Busy
LD 0
N
ST 0
Y
Address
[R1]
DIV 연산 결과 반영
Register result status
clock
F0
F1
F2
F3
16
M(1)
M(2)
ALU 0
M(3)
F4
F5
F6
M(4)
F7
F8
M(5)
F9
F10
Example Cycle 17
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
11
SUB
F6, F3, F10
4
13
15
DIV
F8, F9, F2
5
6
16
ADD
F2, F6, F9
6
17
STORE
F8, [R1]
7
ADD
F1, F3, F4
15
16
Bypass에 1사이클
Reservation Station
Time
Name
Busy
Op
Vj
Vk
Qj
ALU 0
Y
ADD
M(4)
R(F9)
M(4)
ALU 1
Y
ADD
R(F3)
R(F4)
MUL 0
N
MUL 1
N
Qk
Name
Busy
LD 0
N
ST 0
Y
Address
[R1]
DIV의 Broadcasting에 1사이클
Register result status
clock
F0
F1
F2
F3
17
M(1)
M(2)
ALU 0
M(3)
F4
F5
F6
M(4)
F7
F8
M(5)
F9
F10
Example Cycle 18
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
11
SUB
F6, F3, F10
4
13
15
DIV
F8, F9, F2
5
6
16
ADD
F2, F6, F9
6
17
STORE
F8, [R1]
7
18
ADD
F1, F3, F4
15
16
18
Reservation Station
Time
Name
Busy
Op
Vj
Vk
ALU 0
Y
ADD
M(4)
R(F9)
ALU 1
N
MUL 0
N
MUL 1
N
Qj
Qk
Name
Busy
LD 0
N
ST 0
Y
F7
F8
Address
[R1]
Register result status
clock
F0
F1
F2
F3
18
M(1)
M(8)
ALU 0
M(3)
F4
F5
F6
M(4)
M(5)
F9
F10
Example Cycle 19
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
11
SUB
F6, F3, F10
4
13
15
DIV
F8, F9, F2
5
6
16
ADD
F2, F6, F9
6
17
19
STORE
F8, [R1]
7
18
19
ADD
F1, F3, F4
15
16
18
우선순위에 따라 STORE 먼저 처리
Reservation Station
Time
Name
Busy
Op
Vj
Vk
ALU 0
Y
ADD
M(4)
R(F9)
ALU 1
N
MUL 0
N
MUL 1
N
Qj
Qk
Name
Busy
LD 0
N
ST 0
N
F7
F8
Address
Register result status
clock
F0
F1
F2
F3
19
M(1)
M(8)
ALU 0
M(3)
F4
F5
F6
M(4)
M(5)
F9
F10
Example Cycle 20
Instruction status
IS
EX
WR
ADD
F0, F1, F2
1
2
5
LOAD
F1, [R1]
2
3
4
MUL
F3, F5, F0
3
7
11
SUB
F6, F3, F10
4
13
15
DIV
F8, F9, F2
5
6
16
ADD
F2, F6, F9
6
17
20
STORE
F8, [R1]
7
18
19
ADD
F1, F3, F4
15
16
18
Op
Vj
Vk
Reservation Station
Time
Name
Busy
ALU 0
Qj
Qk
Name
Busy
N
LD 0
N
ALU 1
N
ST 0
N
MUL 0
N
MUL 1
N
F7
F8
Address
Register result status
clock
F0
F1
F2
F3
20
M(1)
M(8)
M(6)
M(3)
F4
F5
F6
M(4)
M(5)
F9
F10