Transcript ROD FDR / PRR Firmware Overview • Introduction • Design Overviews

ROD FDR / PRR
Firmware Overview
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25/05/2016
Introduction
Design Overviews
Device Utilisation
Firmware Management
Conclusion
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Introduction
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18 G-links
Input FPGA
– Data formatting & buffering
INPUT
FPGA
Switch FPGA
– buffering, packet building & S-link control
Monitor FPGA
– VME-accessible RAM
– (PCI to daughter card & embedded PC core)
VME FPGA
– motherboard registers, chip selects
VME
FPGA
INPUT
FPGA
INPUT
FPGA
SWITCH
FPGA
VME
CPLD
To 4
S-Links
INPUT
FPGA
INPUT
FPGA
MONITOR
FPGA
VME CPLD
– DTACK, BRDSEL, Reset register
& System ACE Control
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Input Firmware Variants
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13 variants of Input FPGA firmware required
– different data sources; compression levels; neutral
Compiled into 8 System ACE collections:
ACE
ROD Type
Address
0
PPM DAQ
Uncompressed
1
PPM DAQ Compressed
2
PPM DAQ
Super-compressed
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CP DAQ
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JE DAQ
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CP RoI
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JE RoI
7
Neutral
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INP firmware varients
PPM Uncompressed
PPM Compressed
PPM Supercompressed
CPM DAQ + CMM CP DAQ
JEM DAQ + CMM JE DAQ
CPM RoI
JEM RoI + CMM JE RoI
Neutral
Only Input FPFA firmware differs between variants
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Input FPGA Overview
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Input FPGA divided into 2 blocks:
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Formatting Logic
– front-end data processing
– specific to given Input FPGA variant
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Input FPGA
Formatting
Logic
Common
Logic
Common Logic
– back-end interface to Switch FPGA
– common to all Input FPGA variants
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Input FPGA - Formatting Logic
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13 f/w variants required for
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Subslice suppression
Zero suppression
GLink
DAV
GLink DAV
Debounce
Control
Logic
GLink
Data
Serial/Parallel
Conversion
Data
Formatting
Suppression
Write
Enable
Error checking
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Control
Signals
X4
Suppression
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1 Neutral format
10 Native formats (without compression)
2 Compression formats (see next slide)
GLink down
GLink protocol error
GLink parity error
LVDS link error
BCN mismatch
Error
Checking
FIFO
Data
Error
Maximizing data throughput
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1 tick DAV gap for native formats
3 ticks DAV gap for neutral format
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Input FPGA – PPM Compressed Formatting Logic
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Input data from
1 G-link = 1 PPM
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B
B
B
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Requires more resources than other formats
Data arrive serially 1 ASIC / G-link pin
Rotation, buffering (BlockRAM)
MUX to compression algorithm 1 channel / time
Lossless compression: deviations from minimum value
of channel
Variable length bit fields
Most efficient of 6 encoding schemes applied to channel
Requires PPM data of 1 LUT + 5 FADC slices
Noise dominates data – compression tuned for this
Compression algorithm well tested in physics
simulation: 70% data reduction c.f. requirement = 46%
Output = bit-stream chopped into as many S-link words
as required
ASIC 15
ASIC 2
ASIC 1
ASIC 0
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B
A
B
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Buffer
Compression
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No hardware testing or simulation of complete FPGA
Device utilization is a concern, but optimization seems
likely
PPM Super-Compressed very similar architecture: data
thresholded before compression
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bitstream
bitstream
bitstream
Common Logic
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Input FPGA – Common Logic
Data buffering
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Event Manager FIFO stores event lengths &
error flags
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Handshake to Switch
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Generates status words for overflowed &
missing (timed-out) event packets
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Recovers from error conditions without
intervention
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All FIFOs have programmable BUSY thresholds
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Data & EvtMng FIFOs built from BlockRAM
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BCN FIFO distributed RAM
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Clock domains crossed only by asynchronous
FIFOs
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x4
Formatting Logic
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Switch clock
domain
Common Logic
Overflow /
timeout
Data
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Data
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Data FIFO (8k)
wen
Error
Flags
BCN
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Cntr
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Local
VME
EvtMng
FIFO (512)
Buffer
Ctrl
BCN FIFO
(16)
Output
Ctrl
Switch FPGA
G-Link clock
domain
ROD Busy
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Switch FPGA
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Cascaded switch structure
3 Slink routing configuration
5 Input FPGAs
4 Output Slinks
Over 100 combinations
Complex flow control
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Synchronize 5 input FPGAs,
4 SLinks and 1 TTC stream
Input FPGA0
Input FPGA1
Input FPGA2
Slink Data
Assembling
SLink0
Slink Data
Assembling
SLink1
Slink Data
Assembling
Input FPGA3
Slink Data
Assembling
Input FPGA4
Copy
Mode
SLink2
SLink3
Complicate timeout behaviour
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GLink timeout
TTC trigger type timeout
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Switch Control
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TTC Info control
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Switch FPGA – Slink routing mode 0
Input FPGA0
Input FPGA1
Input FPGA2
Input FPGA3
Input FPGA4
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Slink Data
Assembling
SLink0
Slink Data
Assembling
SLink1
Slink Data
Assembling
SLink2
Slink Data
Assembling
SLink3
Input FPGA0
SLink0
Input FPGA 1
SLink1
Input FPGA 2
SLink2
Input FPGA 3 & 4
SLink3
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Switch FPGA – Slink routing mode 1
Input FPGA0
Slink Data
Assembling
SLink0
Slink Data
Assembling
SLink2
Input FPGA1
Input FPGA2
Input FPGA3
Input FPGA4
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Input FPGA 0 & 1
SLink0
Input FPGA 2 & 3 & 4
SLink2
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Switch FPGA – Slink routing mode 2
Input FPGA0
Slink Data
Assembling
SLink0
Input FPGA1
Input FPGA2
SLink2
Input FPGA3
Input FPGA4
Input FPGA 0 & 1 & 2 & 3 & 4
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Slink 0 & 2
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Monitor FPGA
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Receives data from Switch FPGA, copied from Spy buffers
– 4 x Rocket IO transceivers (total 4 Gbit/s) (untested)
– 20 x160 MHz point-point links (3.2 Gbit/s)
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Can process data for monitoring purposes
– 2 CPUs in FPGA (XC2VP20) + external instruction RAMs
– PCI interface using commerical core (33 MHz, 64 bit) to PMC daughter board (untested)
– interface to external Dual-Port RAM (64K x 32) with VME access (untested)
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Monitor FPGA intended to provide capacity for monitoring as need arises
As yet firmware undeveloped as no clear requirement has been identified
Current firmware consists only of VME interface, data links to Switch FPGA
and interface to Dual Port RAM.
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VME CPLD & FPGA
VME CPLD
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Implements key VME functions:
– DTACK, BRDSEL, Reset register & System ACE Control
VME access to board possible if FPGAs fail to configure & configuration can be initialised
VME FPGA
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Generates chip select signals
Implements motherboard Register map
I2C interface to TTCrx
Access to System ACE internal registers
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Device Utilisation (1)
VME CPLD
- XCR3384XL
Macrocells:
Pterms:
Registers:
Pins:
Fn Block Inputs:
VME FPGA
- XC2VP20-5ff896
Slice Registers:
4 input LUTs:
IOBs:
Block RAMs:
114/384 =
148/1152 =
48/384 =
145/208 =
161/960 =
242/18,560 =
399/18,560 =
266/556 =
1/88 =
30%
13%
13%
70%
17%
1%
2%
47%
1%
Switch
- XC2VP30-5ff896
Slice Registers:
4 input LUTs:
IOBs:
Block RAMs:
4,743/27,392 =
6,491/27,392 =
463/556 =
60/136 =
17%
23%
83%
44%
Input FPGA, all except PPM compressed
- XC2VP20-5ff896
Slice Registers: 3,096–7,799/18,560 = 16–42%
4 input LUTs:
5,021–8,415/18,560 = 27–45%
IOBs:
264/556 =
47%
Block RAMs:
64/88 =
72%
Monitor FPGA
- XC2VP20-5ff896
No figures available
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Device Utilisation (2)
Input FPGA, PPM compressed
- XC2VP20-5ff896
Slice Registers:
9,258/18,560 =
4 input LUTs:
15,330/18,560 =
IOBs:
262/556 =
Block RAMs:
84/88 =
49%
82%
47%
95%
Input FPGA, PPM compressed
- XC2VP30-5ff896
Slice Registers:
9,258/27,392 =
4 input LUTs:
15,330/27,392 =
IOBs:
262/556 =
Block RAMs:
84/136 =
33%
55%
47%
61%
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– current device
– footprint compatible alternative
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Firmware Management
Design Team
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James Edwards, Ian Brawn, Weiming Qian, Adam Davis, Dave Sankey
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Areas of responsibility with well-defined interfaces
Design Tools
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FPGAdvantage: HDL Designer, Modelsim, Precision Synthesis
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XISE (+ EDK)
Version Control
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Synchronicity used for version control, archiving & file sharing; archive @ RAL
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May move to CVS @ CERN when firmware more stable
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Each FPGA design has incremental revision number – file name & readable from VME
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Log in VHDL: who, when, what
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System ACE collections have incremental revision numbers
Distribution
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via web page
– Full history, log & instructions for building ROD collections
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May place collections in EDMs when stable
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Conclusion
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Most firmware well developed
– Confident further changes will be tweaks rather than major rethinks
Except Input FPGA for PPM Compressed code, devices have plenty of spare
capacity for logic changes
Working practices in place will benefit us after production
Some development of firmware still required, particularly PPM Compressed logic
– Test
– Reduce device utilisation
Monitor FPGA undeveloped due to no current requirements
– Exists to provide spare resources which may prove useful later
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