Transcript APPLIED SIGNAL PROCESSING AND IMPLEMENTATION Introduction to 9 & 10th semester Fall 2005

APPLIED SIGNAL PROCESSING
AND IMPLEMENTATION
Introduction to 9 & 10th semester
Fall 2005
Outline
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2.
3.
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6.
7.
Basic ASPI Model (A3)
Trends from S8 -> S9 -> S10
Course overview
Project work
Reading suggestions
Formation of project groups
Group Rooms, Schedule, Home Page etc
ASPI Introduction
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A3 Paradigm
Applications
1
Algorithms
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5
Architectures
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3
Application: Non-Linear Signal Processing etc.
1. Algorithm selection
2. Simulation
3. Architecture selection and modelling
4. Design Space Exploration
5. HW/SW Co-Design
ASPI Introduction
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Basic ASPI Model (A3)
Applications
Algorithms
Architectures
For each application
=> many candidate algorithms
For each algorithm
=> many implementation architectures
=> Large no. of solutions => Large Design Space
ASPI Introduction
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Focus of S8ASPI
Applications
1
Algorithms
Architectures
2
3
1. Application to Algorithm Transformation
2. Simulation & Implementation Environments
ASPI Introduction
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Focus of S9 ASPI
Applications
1
Algorithms
Architectures
4
5
2
1. App -> Alg: Non-Linear Signal Processsing and others
2. Simulation
4-5.Alg  Arch:HW/SW Codesign and Architecture Exploration
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Focus of S10 ASPI
Applications
Algorithms
Architectures
1. Proving your potential for R&D
2. Closing the loop
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9th Semester
Applied Signal Processing and Implementation
THEME:
Non-linear DSP Methods and Real-Time Architectures
PERIOD:
1 September – 31 January
PURPOSE:
To enable the students to understand, analyze, and employ state-of-theart DSP methods and algorithms, for example in the domain of non-linear
techniques.
To enable the students to apply theories and methods
to select, analyze and evaluate heterogeneous DSPprocessor architectures given a DSP functionality
under the constraint of some cost function.
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Putting it all together
8.sem
Design Methodology
9.Sem
Algorithm analysis
SW Platform analysis
HW Platform analysis
SW compilers
HW compilers
Design Space Expoloration
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9th Semester Courses
S9 Theme: Non-linear DSP Methods and Real-time Architectures
FP9-2
Discrete-Time Kalman Filtering
2 ECTS
SE/KB
ASPI9-2A
ASPI9-2B
ASPI9-3
ASPI9-4
Mob9-2
HW/SW CoDesign
HW Platform Analysis, Comp. & Optim.
Non-linear Signal Processing
Neural Networks
Radio Communication III
2 ECTS
2 ECTS
2 ECTS
1 ECTS
1.4 ECTS
PE/YM/PK
PE/YM/PK
PE/PR
EL/UH
EL/FF
Project
22 ECTS
S10 Master Thesis in Applied Signal Processing and Implementation 30 ECTS
EL : ELective Course
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Project Work Overview
Project Development Model
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2.
3.
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5.
6.
Application domain study
Algorithm Development and Simulation
Design Space Exploration
Implementation
Evaluation of results
Next step
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Project Work Overview
Project Development Model
1.
2.
3.
4.
5.
6.
Application domain study
Algorithm Development and Simulation
Design Space Exploration
Implementation
Evaluation of results
Next step
ASPI Introduction
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HW/SW Co-Design: generic flow
ASPI Introduction
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Project Work Technology
Platform:
Components:
Lang.:
Property:
PC
FPGA
Pentium Proc.
Sync. Logic PE’s
Soft Proc.
Hard Proc.
C
HandelC
C
C
Seq, Gips, 100 W
Par, ??, ??
Seq, Mips, ??
Seq, Mips, ??
FPGA
Supplier:
Xilinx
Components:
Lang.:
Property:
MicroBlaze Proc.
PowerPC
NIOS
ARM
Sync. Logic PE’s
C
C
C
C
HandelC
32 bit RISC
32 bit RISC
16 bit RISC
16/32 bit RISC
”Anything”
Altera
Xilinx,
ASPI
Introduction
Altera
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Project Work Content
• 2 conventional processor platforms
• 2 languages
• Complex Design Software
=> Keep projects simple(at first)
Generic project example:
Design, implement and test a processor/coprocessor
architecture, that speeds up the execution of a selected
algorithm or eventually a family or a set of algorithms
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Project Work Content
An example can be found in:
Accelerating C Software Applications
Results:
FPGA, 50MHz w/o I/O .71
FPGA, 50MHz with I/O 15.61
Pentium, 3.6GHz
0.64
PPC405, 400MHz
24.20
Iterations
100
Acceleration (@10K iterations)
3.03 4.69
16.48 144.71 147X
15.47 15.32 22.74 149.40 106X
2.51 5.32
23.11 199.55 104X
242
484
2418
n/a
1
1000 2000 10000 100000
Notes:
Figure 5. Test results for a range of maximum iteration values demonstrate substantial speedup of
the algorithm (167X when using two parallel processes) compared to an embedded processor
implementation.
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Project Work Content
Specific project examples:
1. Vector Co-processor (next pages)
2. Active Noise Cancellation in Headsets, Per Rubak
3. Any suitable algorithm, that you/we may suggest
1. GSM Vocoder (Ch. 5 in SpecC book)
2. H263 Video Decoder (prev. S10 project)
3. RS codec for DVB-H (prev. S10 project)
4. Digital Camera example (Ch. 7 in Vahid’s book)
5. Video filtering
6. 3GDSP algorithm examples
7. A.s.o.
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Vector Inner Product (1)
c = aTb
Ex. (3 elements)
(a transposed times b)
c is a scalar, a and b are vectors (real valued)
a = [a1, a2, a3]T
b = [b1, b2, b3]T
c = a1*b1 + a2*b2 + a3*b3;
Pseudo code
acc = 0;
for i=1:3,
acc = acc + a[i]*b[i];
end;
c = acc;
Parallelism, Control & Communication
How to combine with NIOS/MicroBlaze
When is it beneficial
etc
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Vector Inner Product (2)
Example algoritms
FIR filter
a represents the filter coefficients
b represents the buffer of the signal to be filtered
c represents the filtered signal
Matrix multiplication may be described as a set of
vector inner products.
Several matrix operations may be described
as sets of vector operations.
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Project Work Details
Application/Algorithm
Implementation(s)
SW (PC/AD/ARM) HW(Xilinx/Altera)
Implementation
SW + HW
MicroBlaze/NiosII + Co-processor
Implementation Analysis
(Partial) design methodology
Application/Algorithm Analysis
Implementation Analysis
Suggestions for HW/SW partitioning
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Project Work Results
ASPI Introduction
See also slide
21
Lab Resources
Available platforms:
1. 2 RC100 boards (“small” Xilinx FPGA),
2. 2 RC203 boards (“medium” Xilinx FPGA),
3. 2 Altera boards (“medium” Altera FPGA),
4. TI and AD DSP boards (model ? quantity ?),
5. 1 Lyrtech Signal-Master board (FPGA+DSP, no support!!!)
Available development tools:
1. Celoxica DK3 design tools
2. Xilinx & Altera design tools
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Reading suggestions/Articles
Closely Coupled Co-processors for Algorithmic Acceleration
Accelerating C Software Applications
Applications of Reprogrammability in Algorithm Acceleration
Algorithmic C Synthesis Fuels Functional Reuse
Using Hardware Acceleration Units in
Software Defined Radio Modem Functions
Finding the best System Design Flow for a High-Speed JPEG Encoder
From C software to FPGA hardware
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Reading suggestions/Books
1. SpecC: Specification Language and Design Methodology
2. System: Design: A Practical Guide with SpecC
See also SpecC System
3. Embedded System Design:
A Unified Hardware/Software Introduction
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Formation of project groups
1. Study project ideas carefully
2. Discuss with teachers
3. Prepare for Sept. 14th. a specific project proposal and a list
of participants
4. Present your proposal at the next semester group meeting
to be held at ???
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ASPI Group Rooms, Home Page etc
Group Rooms:
9ASPI 12 studerende i 1 grupperum
RUM:
A6-108/ 36 m2
Home Page:
http://kom.aau.dk/~dsp/aspi05-02/sites/default/
Secretary:
Dorthe Sparre
Fredrik Bajers Vej 12, A5-214
Phone: +45 9635 8616
E-mail: Dorthe Sparre <[email protected]>
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9th Semester Courses
ASPI9-2A Hardware/Software Codesign
Purposes:
1. Give the students the essential knowledge about problems related to
the design of modern digital systems for various applications,
in particular mobile applications.
2. Make the students understand how to apply digital electronic
components efficiently in such systems.
3. Make the students able to apply a systematic design methodology to
arrive at near-optimal implementations, using design tools for
evaluating a large number of alternatives
(Design Space Exploration, DSE).
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9th Semester Courses
ASPI9-2B Hardware Platform Analysis, Compilation, and
optimization
Purposes:
1. To provide the students with:
knowledge about one particular state-of-the-art IC technology, and
comprehension about its usage in modern integrated system design.
2. To make the students understand and apply methods for synthesizing from a functional description to an optimal heterogeneous
architecture in terms of physical size, execution time, and power
consumption.
3. To provide comprehension on syntax and semantics of a specific
modern Hardware Description Language (HDL).
4. To make the students able to apply the above topics in terms of
formal methods for structures HW/SW Codesign.
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