Transcript Performance of Snooping Protocols Kay Jr-Hui Jeng

Performance of
Snooping Protocols
Kay Jr-Hui Jeng
Outline
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Snooping protocols
Simulation results
Comparison of performance
Conclusion
Snooping protocols
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a protocol for maintaining cache coherency in
symmetric multiprocessing environments. In a
snooping system, all caches on the bus snoop the bus
to determine if they have a copy of the block of data
that is requested on the bus. Every cache has a copy of
the sharing status of every block of physical memory it
has. Multiple copies of a document in a multiprocessing
environment typically can be read without any
coherence problems; however, a processor must have
exclusive access to the bus in order to write.
Comparisons of
Write-invalidate & Write-update
Write-invalidate
Write-update
Writing
Writing processor
forces all others to
invalidate their copies
Writing processor
forces all others to
update their copies
Advantage
Less bus traffic
Other processors can
get the data faster
disadvantage
Update the data to
cache slower
Higher bus traffic
Comparisons of
Write-back & Write-through
Write-back
Write-through
Writing
The memory is
The memory is
updated only when the updated every the
block in the cache is
cache is updated
being replace
Advantage
Less bus traffic
disadvantage
Update the data to
memory slower
Memory can get the
new data faster
Every write is
observable-> Simple
Higher bus traffic
Types of Snooping Protocols
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Write-Invalidate and Write-Through
Write-Invalidate and Write-Back
Write-Once
Write-Update and Partial Write-Through (Firefly)
Write-Update and Write-Back (Dragon)
Write-Invalidate and Write-Through
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The memory is always consistent with the most
recently updated cache copy
Multiple processors can read block copies from
main memory safely until one processor updates
its copy. At this time, all cache copies are
invalidated and the memory is updated to
remain consistent.
Write-Invalidate and Write-Through
Write-Hit, Read-Hit
Bus Write-Miss, Bus Write-Hit
VALID
INV
Write-Miss, Read-Miss
Read-Miss
Synapse
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It belongs to write-invalidate & write-back protocol
A multiprocessor for fault-tolerant transaction
processing
It has two system buses, the added bandwidth of the
extra bus allows the system to be expanded to more
processors (max 28)
The including single-bit tag with each cache block in
main memory =>whether main memory is to respond
to a miss on that block
Synapse
Write-Once
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Write-invalidate protocol (Goodman)
Designed for single-board using Multi-bus
Combination of Write-through and Write-back
Write-Once
Write-Update and Partial Write-Through
(Firefly)
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An update to one cache is written to memory at the
same time; Broadcast to other caches sharing the
updated block
These caches snoop on the bus and perform updates to
their local copies.
There is also a special bus line, which is used to detect
sharing
Multiple writers are permitted-the data for each write to
a shared block are transmitted to each and to the
backing store =>The protocol never causes an
invalidation
Write-Update and Partial WriteThrough (Firefly)
Write-Update and Write-Back
(Dragon)
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It similar to write-update and partial write
through
Memory updates are done only when the block
is being replaced
Writes to shared blocks are not immediately sent
to main memory, only to other caches that have
a copy of the block
Write-Update and Write-Back
(Dragon)
Experiment Results (1)
Experiment Results (2)
Experiment Results (3)
Experiment Results (4)
Experiment Results (5)
Result analysis (1)
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F-7: Dragon and Firefly protocols are identical
in the handling of private blocks. The
performance of write-once is dependent on the
trade-off between single word writes and the
reduction in the write-back. The performance of
Synapse is below the others as a result of the
additional overhead of treating write hits on
unmodified block as write misses.
Result analysis (2)
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Comparison of F-8~F-10 with F-7 indicates the impact
of handling shared blocks efficiently
F-8, F-11 and F-14 (share block=16), which
demonstrate that the distributed write approach of
Dragon and Firefly has the best performance in the
handling of shared data.
F-11, F-12 and F-13: Because no invalidations, the
performance of Dragon and Firefly decreases as the
average actual sharing decreases and the number of
shared blocks increases.
Result analysis (3)
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The performance of the Dragon exceeds that of
the Firefly at levels of high sharing(F-8 and F-9)
because the Firefly must send distributed writes
to global memory while the Dragon sends them
to the caches only.
The performance of write-once is lower than
above protocols as a result of the added
overhead of updating memory each time a Dirty
block is missed in another cache.
Result analysis (4)
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The performance of Synapse is lower, because it
increased overhead of read misses on blocks
that are Dirty in another cache and to the added
overhead of loading new data on a write hit on
an unmodified block.
The results of Write-Invalidate and WriteThrough which has the lowest performances,
because blocks are not loaded into the cache on
a write miss.
References
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Hesham El-Rewini, Mostafa Abd-El-Barr. Advanced
Computer Architecture and Parallel Processing, John Wiley,
2005.
James Archibald and Jean-Loup Baer. Cache Coherence
Protocols: Evaluation Using a Multiprocessor
Simulation Model. ACM Transactions on Computer Systems,
Vol. 4, No. 4, November 1986, 273-298(1986).
http://www.webopedia.com/TERM/S/snooping_prot
ocol.html
References
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https://www.cs.tcd.ie/Jeremy.Jones/vivio/caches/write
OnceHelp.htm
http://cswww.bu.edu/faculty/best/crs/cs551/lectures/lecture12.html
http://cs.engr.uky.edu/~manivann/Spring2005/cs570/
ch5-6.pdf
www.cs.berkeley.edu/~pattrsn/252F96/Lecture18.pdf
http://www.eng.tau.ac.il/~arch/LECTURES/Lecture1
.pdf
Thank You!