Transcript CMPT 250 Computer Architecture

Instructor: Yuzhuang Hu
[email protected]
Design strategy in ASM
CISC Architecture
 The goal of the CISC architecture is to match more closely
the operations used in programming language and to
provide instructions that facilitate compact programs and
conserve memory.
 A purely CISC architecture has the following properties:
 Memory access is directly available to most types of
instructions.
 Addressing modes are substantial in number.
 Instruction formats are of different lengths.
 Instructions perform both elementary and complex
operations.
Combined CISC-RISC Organization
Instruction fetch
Microprogram counter
Decode and operand
fetch
Control ROM
Execute
Write-back
CISC CPU Instruction Formats
31
25 24 20 19
15 14
10 9
0
Three register type
OPCODE
DR
SA
Two register type
OPCODE
DR
SA
Immediate
Branch 1
OPCODE
DR
SA
Large target offset
Branch 2
OPCODE
DR
SA
SB
SB
Short target offset
Micro-programmed Control
SA CA CA-1
MS
MI
+1
0
1
2
Mux E
3
MZ
MZ-1
PS
Z
ME
MC
Address
Microcode ROM
Data
MZ
CA
DOF
EX
MZ-1
CA-1
Address Control
Inputs
Outputs
Register Transfer Due to Me
MZ-1 MZ
MI PS
Z ME1
ME0
MS
11
01
X
0
0
0
0
1
PS∙Z: MC <- MC+1
11
01
X
0
1
0
1
1
PS∙Z: MC <- CA-1
11
01
X
1
0
0
1
1
PS∙Z: MC <- CA-1
11
01
X
1
1
0
0
0
PS∙Z: MC <- MC+1
0x
01
X
X
X 0
0
1
MC<-MC+1
x0
01
X
X
X 0
0
1
MC<-MC+1
xx
00
0
X
X 1
0
0
MC<-CA
xx
00
1
X
X 0
1
1
MC<-ST
xx
10
X
0
X 1
0
0
PS: MC<-CA
xx
10
X
1
X 1
0
1
PS:MC<-CA
xx
11
X
X
X 0
0
1
MC<-MC+1
Load Indirect Indexed(LII)
Microinistructions
Action
Add M C
ress Z A
R DX M BS
W
D
P M F L M
S W S C A
M A
B X
BX C
X
R16<R[SA]+zf IML
LII0
01 00
1
10
0 00
0 0
2 0 00
1
00
00
00
MC<-MC+1
(NOP)
LII1
01 00
0
00
0 00
0 0
0 0 00
0
00
00
00
R17<-M[R16]
LII2
01 00
1
11
1
00
0 0
0 0 00
0
10
00
00
MC<MC+1(NOP)
LII3
01 00
0
00
0 00
0 0
0 0 00
0
00
00
00
R[DR]<M[R17]
LII4
10 ID 1
LE
01
1
0 0
0 0 00
0
11
00
00
00
A Personal Computer
Screen
Hard drive
Keyboard
Drive
Controller
Graphics
Adapter
Bus Interface
Processor
CPU, FPU, MMU
Internal Cache
RAM
External
Cache
Access Times
 Cache: 1 ns, memory: 10 ns, hard drive: 13 ms
 Assume that 95% of the fetches will be from a cache
and about 4.999995 percent of the fetches will be from
main memory. The average access time then is:
 0.95*2+0.49999995*10+5*10-8*1.3*107=3.05ns
Locality of Reference
 Temporal Locality: refers to the relative times at which
instructions and operands are accessed.
 Spatial Locality: refers to the relative locations at
which they reside in main memory.
Write Methods
 Write the result into main memory. This is also called
write-through.
 Write the result into the cache if there is a cache hit.
This is also called write-back.
 write-allocate: when a cache miss happens, read the
line containing the word to be written from main
memory into the cache, with the new word written into
both the cache and main memory. Dirty bit of a line.
THANKS!