ATLAS TRT Front End Electronics

Mitch Newcomer for the ATLAS TRT collaboration

TRT Physical Layout

430,000 Straw Tube system TRD 2005 2

Straw Sensor Characteristics

• Gas  • Gain  70% Xenon / 27% C0

2

2X10

4

(55us) Useable / 3% Oxygen 3X10

3

(5ns) • Wire Resistance  80 Ω/m Length 30, 50, 70cm • Cathode  4mm diameter HV ~ -1300V • Rate  Ionizing Particles / Second / wire up to 18MHz Lemo Barrel Straw Cathode TRD 2005 3

Design Goals

Physical Objective Electronics Implementation Track Resolution < 140um High Efficiency for Transition Radiation Detection Low Power – all TRT heat must be removed.

a) Trigger on signal from earliest primaries. Min threshold ~ 2fC for gas gain of ~20,000 b) 1ns Leading Edge timing c) Fast Shaping ~5ns t peak a) 10 – 14ns t and reflection in un terminated straw peak to include signal b) Threshold Range ~ 140fC Work at lowest power consistent with required performance.

TRD 2005 4

Signal rate Radiation Tolerance L1 Readout Rate L1 Pipeline Depth

Design Goals

18MHz 10MRad 10 14 N/cm 2 100KHz >3us

TRD 2005 5

Technology Choices

High Rate High Density Low Power Detector Mounted ASIC design Commercially Available or Special Process?

Radiation Hardness?

Special Analog Process  DMILL Digital Commercial ¼ μm CMOS CERN Layout Rad Tolerant Library How much Functionality / ASIC Rad Hard BiCMOS? All sub um CMOS?

Fast Low Power Analog  Bipolar Low Power High Density Digital  CMOS Differential Low Level Signals off and on board

ASIC Yield

= π [

Y all blocks

] Uncertain yield led to the split of Analog and Digital ASIC functionality

DTMROC .25um CMOS and ASDBLR (DMILL bipolar)

TRD 2005 6

A

SDBLR Implementation

• Analog Gain ~ 18mV/fC at Comparator input. • Double Pulse Resolution ~ 25 – 50ns dependent on 1

st pulse amplitude.

• Spontaneous on det.Trigger Rate at 2fC threshold <300KHz. • High Threshold Maximum Range 

140fC.

• Power ~ 40mW/ch. • Preamp Input protection ~ 2.8mJ. • Ternary (comparator) output levels (nominal Design):

Signal Quiescent Track only Track & TR Tern Pos 400uA 200uA 0uA Tern Neg 0uA 200uA 400uA

TRD 2005 7

A

SDBLR Implementation

• Process - Rad Tolerant 0.8um BiCMOS Technology (DMILL) • Designed at the discrete device level using SPICE for Simulation • Channel Complexity – 160 Bipolar Transistors / 10 CMOS Switch – 160 Resistors / 105 Capacitors • Channel based Layout – Avoided metal runs over transistors/resistors. – Double vias where possible. – Separated Analog and Comparator/Ternary Driver Power – Dedicated power bus distribution at the channel level. – Substrate Contact and Power buss isolation between ch. – Preamp Supply filter on each channel. • Eight (nearly) identical Channels on 340um Pitch. TRD 2005 8

Transition Radiation

Shaping for Energy Measurement Simulated Response 50cm Straw 38 Ω wire Far Near

Tracking Shaper

5ns Peaking

(far-near)/far = .36

Far end of straw Unterminated.

Amp •Longer Shaping allows processing of the prompt and reflected signal in the unterminated straw. •A 2X improvement is realized by using a 12ns shaping time.

TRD 2005

(far-near)/far = .

Near

18

9

ASDBLR Papers

•

NSS00 - Implementation of the ASDBLR Straw Tube Readout ASIC in DMILL Technology

N. Dressnandt, Member IEEE, N. Lam, F.M. Newcomer, Member IEEE, R. Van Berg, Member IEEE, and H.H. Williams

•

NSS02 Radiation Hardness: Design Approach and Measurements of the ASDBLR ASIC for the ATLAS TRT

Nandor Dressnandt, Mitch Newcomer, member IEEE, Ole Rohne and Steven Passmore

TRD 2005 10

Full Readout With Custom ASICS

Low Level (30mVStep) Ternary inputs Chip to Chip LVDS (like) Clock/Control Chip to Back End

16 Channel Readout ASIC Triplet Ternary Encoding saves ~ 1.4million connections

TRD 2005 11

Implementation of the DTMROC-S ASIC for the ATLAS TRT Detector in a 0.25µm CMOS technology

NSS Norfolk, Virginia November 10-16, 2002

V.Ryjov

JINR, Moscow, Russia and University of Lund, Lund, Sweden

F.Anghinolfi, Ph.Farthouat, P.Lichard

CERN, Geneva 23, Switzerland

R.Szczygiel

CERN, Geneva 23, Switzerland and INP, Cracow, Poland

N.Dressnandt, P.T.Keener, F.M.Newcomer, R.Van Berg, H.H.Williams

University of Pennsylvania, Philadelphia, USA

T.Akesson, P.Eerola

University of Lund, Lund, Sweden

[email protected]

TRD 2005 12

DTMROC functional Blocks

V. Ryjov ( CERN) TRD 2005 13

• • •

DTMROC DAC’s

(8/ASIC) Threshold Setting, Board Voltage Sensing, Temp Sensing Test Pulse Amplitude Setting

Internal bandgap reference 1.26V

Current mirror master - 128 PMOS unit devices (L=8um,W=5um) 256 identical PMOS slave current mirrors per DAC

TRD 2005 14

Analog Signal in ASDBLR Ternary Output of ASDBLR

What we Readout

Adjustable TR Threshold Adjustable Track Threshold 40MHz Clock 25ns DTMROC Data Each straw

Track TR

Actual 27 Bits per Straw All Straws Readout each L1 L1 3us later Pipeline Data Storage TRD 2005 3.1ns / bit 24 time bits 3 TR bits 15

Repetitive Test Pulse Measurement 100 test pulse triggers at each threshold DAC value Time Bin bit Number (3ns/bit) TRD 2005 16

ASIC Packaging

Custom Fine Pitch Ball Grid Arrays

16 Channel DTMROC ASDBLR 8channel ASDBLR 8channel TRD 2005 17

ASIC Test Results

• 139K ASDBLR’s tested Yield: 72% Functional Yield 57% after parametric selection

Pushed into Wide, asymmetric cut due to process matching problems ( -140mv

• 46K DTMROC’s tested Yield: 77% main digital test 67% after parametric selection TRD 2005 18

Threshold Sensitivity

(test beam measurements) Position Resolution Efficiency Lowest Accepted Threshold Offset Lowest Accepted Threshold Offset Nom operating Point TRD 2005 Nom operating Point 19

End Cap Wheel Readout

TRD 2005 20

End Cap Wheel Electronics

Layered Analog and Digital Approach Time Digitizing / Digital Readout /Output Analog Signal Processing Board Output Cable Board 4 X DTMROC 8X ASDBLR Inputs to End Cap Wheel “tread”

TRD 2005 21

B wheel “readout tread”

32 Straws Fujitsu Connector 192 Channel DTMROC Board Readout Cable Connector Flexible Jumpers

TRD 2005

B wheel ASDBLR Board

22

Barrel Readout

> 2X Endcap density • 5 2,000 axial straws •4 mm X 140cm cathode •2 •R anode wires glass bead separator eadout on each end.

TRD 2005 23

Barrel Module Readout Array

16 Straw Anode sockets 6 Analog Reference

TRD 2005 24

Stamp Board Approach

16 Channel ASIC triplet Readout

Stamp FLEX Boards Kapton Connection DTMROC in TQFP Output Roof Connector Chip on Board ASDBLR’s TRD 2005 25

Stamp Board Threshold Scans

TRD 2005 26

Signal Return Path

External currents added in signal return path can seriously corrupt straw signal.

Ideal

Signal Return

ASD Preamp



Agnd



Connector pins



Straw Anode Pins



HV CAP



Straw Cathode

Cable Shield currents, Dgnd bounce noise Other Conductors These currents may be redirected over a large area by adding a low impedance network of conductors at the end of the module.

TRD 2005 27

Single Analog and Digital Board Approach

Module 1 Small Triangle (one of 12 Custom Barrel Designs) Data Cable Connector (Unstuffed)

Access along All Edges to Analog GND Encloses Detector Ends

Top Side Digital Under side Analog DTMROC ASICS Straw Pin  Floating Contact (NAIS) Connector Input Protection Board(s) 16 Straw modularity 1 of 10 Boards Shown TRD 2005 ASDBLR ASICS underside 28

Triangle Board Threshold Scans

TRD 2005 29

Problem Location (#3)

Position 3 Active Roof for Module 2 75ns total Width

Beam Clock Syncronous Time Bin

TRD 2005

3.1ns /Bin

30

Measured Clock Pickup Threshold 50% min-max 100Dac Cnts AR2FS Location #3 Layers 14, 12, 1, and 4 Clock vias, Line 11 Highlighted

ASDBLR DTMROC ASDBLR

TRD 2005 31

AR2FS Location #3 Layers 14, 12, 1, and 4 Clock vias, Lines 11, 14, and 15 Highlighted Measured Clock Pickup Threshold 50% min-max 180 Cnts TRD 2005 32

Blind vias

Improved AR Board Design

• 1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

Stackup ComponentSignal w Gndd Area fill - Gnda at edges Signal Vdd Gndd Signal - Gnda ring at board edge.

Signal (desperation layer) no clocked signals Gnda ring at board edge.

Empty Vee (-3V) Gnda Vcc ( Open under inputs to reduce capacitance) Signal ( threshold test pulse etc.) Gnda Area fill with slots under inputs Input Signal with Gnda Area fill Gnda Analog Components Signal Gnda Area fill TRD 2005 33

Active Roof Layout Side View Single Site

TRD 2005 34

AR2FL Production Board

Analog Side

14 Layer, 4 levels of Blind vias Significant challenge for PCB vendors TRD 2005 35

AR2FL Production Board

Digital Side

TRD 2005 36

AR2FL Merged Analog and Digital Gnds TRD 2005 10 ohm Resistors Digital Gnd Analog Gnd wrap around Edge Plating 37

RF fingers installed on Barrel Support Structure complete Faraday Enclosure TRD 2005

RF Fingers contact Edge plating on board

38

Final Results One Board (2bl)

TRD 2005 39

On and Off Detector 300KHz Threshold DAC setting

Ben Legeyt (Penn) TRD 2005 40

Final Board Design Problem

Type 3 Front Production Board  Hole in Ground & Power Shields Inputs exposed to digital lines.

TRD 2005 41

Threshold Scan

TRD 2005 42

Simple Model of Pickup

Dual Inputs to encourage Common mode Pickup Charge Division Reduces clock pickup to this input.

Hole in Digital Shield Digital Side Clock Noise Similar Pickup to both inputs Added capacitive compensation to dummy input to balance the pickup and make it common mode.

( 5, 15pF ) TRD 2005 43

Before

and After adding Capacitive compensation TRD 2005 44

Compensation Added

On Detector TRD 2005 45

Production Front End Boards

TRD 2005 46

Backend Readout

TRD 2005 47

Test Beam ’04 Measurements Barrel Sector Readout > 95% efficiency 85% within 2.5σ Track Efficiency by layer 135um Resolution Track Resolution by layer Axial Layer Number in increasing TRD 2005 ‘r’ 48

Transition Radiation Measurements e / π Identification TRD 2005 49

Cosmic Triggered Single Track

3328 Straws TRD 2005 Stas 50

Cosmic Trigger Triple Track

TRD 2005 51

Conclusions

• On Detector TRT Design Goals Achieved exploiting 2 custom ASICS, with high density packaging and 16 complex PCB designs. • High Bandwidth Analog and Digital PCB Readout realized by controlling current return paths and employing PCB to provide a nearly complete shield of analog readout. • We are looking ahead to system integration with SCT and Pixel TRD 2005 52